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Submodule yosys-src
updated
12 files
+2 −2 | Makefile | |
+46 −1 | frontends/verific/verific.cc | |
+5 −0 | kernel/celltypes.h | |
+1 −0 | kernel/constids.inc | |
+108 −0 | kernel/rtlil.cc | |
+7 −0 | kernel/rtlil.h | |
+2 −0 | passes/cmds/Makefile.inc | |
+1,015 −0 | passes/cmds/dft_tag.cc | |
+140 −0 | passes/cmds/future.cc | |
+3 −0 | passes/opt/opt_clean.cc | |
+1 −0 | techlibs/common/prep.cc | |
+70 −0 | techlibs/common/simlib.v |