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Submodule yosys-src
updated
19 files
+2 −2 | Makefile | |
+4 −8 | backends/aiger2/aiger.cc | |
+1 −1 | backends/verilog/verilog_backend.cc | |
+0 −1 | frontends/aiger2/xaiger.cc | |
+30 −23 | frontends/liberty/liberty.cc | |
+4 −0 | kernel/driver.cc | |
+3 −2 | kernel/tclapi.cc | |
+4 −0 | kernel/yosys.cc | |
+4 −0 | kernel/yosys.h | |
+0 −23 | kernel/yosys_common.h | |
+158 −26 | passes/cmds/wrapcell.cc | |
+4 −5 | passes/techmap/abc9_ops.cc | |
+51 −1 | passes/techmap/abc_new.cc | |
+9 −0 | tests/techmap/dfflibmap-sim.v | |
+28 −4 | tests/techmap/dfflibmap.lib | |
+19 −13 | tests/techmap/dfflibmap.ys | |
+0 −23 | tests/techmap/dfflibmap_dffn.lib | |
+47 −0 | tests/techmap/dfflibmap_dffn_dffe.lib | |
+32 −0 | tests/various/wrapcell.ys |