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Submodule yosys-src
updated
14 files
+1 −1 | Makefile | |
+4 −0 | backends/rtlil/rtlil_backend.cc | |
+8 −0 | kernel/calc.cc | |
+1 −1 | kernel/cellaigs.cc | |
+2 −2 | kernel/celledges.cc | |
+3 −2 | kernel/celltypes.h | |
+1 −0 | kernel/constids.inc | |
+1 −1 | kernel/qcsat.cc | |
+165 −2 | kernel/rtlil.cc | |
+22 −0 | kernel/rtlil.h | |
+3 −3 | kernel/satgen.cc | |
+1 −0 | passes/techmap/Makefile.inc | |
+512 −0 | passes/techmap/bufnorm.cc | |
+21 −1 | techlibs/common/simlib.v |