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riscv32i(system_call, csr無し)のパイプラインCPUをVerilogで実装

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YoshizawaShogo/riscv32i_piplined_cpu_verilog

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prerequisite

riscv32-unknown-elf-gccをインストール
iverilogをインストール
パスを通す

usage

$ make update-riscv-tests
$ make isa-test

未対応

CSR命令
ECALL命令
分岐予測 など

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riscv32i(system_call, csr無し)のパイプラインCPUをVerilogで実装

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