HCLK Support

apycula/attrids.py

@@ -1172,6 +1172,70 @@
         'SYNC':             2,
     }
 
+# HCLK
+hclk_attrids = {
+        'BK00DIV2_RST':     0,
+        'BK01DIV2_RST':     1,
+        'BK0MUX0_OUTSEL':   2,
+        'BK0MUX1_OUTSEL':   3,
+        'BK10DIV2_RST':     4,
+        'BK11DIV2_RST':     5,
+        'BK1MUX0_OUTSEL':   6,
+        'BK1MUX1_OUTSEL':   7,
+        'BRGMUX0_BRGOUT':   8,
+        'BRGMUX0_INSEL':    9,
+        'BRGMUX1_BRGOUT':  10,
+        'BRGMUX1_INSEL':   11,
+        'BRGMUX0_BRGSTOP': 12,
+        'BRGMUX1_BRGSTOP': 13,
+        'HCLKDIV0_DIV':    14,
+        'HCLKDIV0_RST':    15,
+        'HCLKDIV1_DIV':    16,
+        'HCLKDIV1_RST':    17,
+        'HSB0MUX0_HSTOP':  18,
+        'HSB0MUX1_HSTOP':  19,
+        'HSB1MUX0_HSTOP':  20,
+        'HSB1MUX1_HSTOP':  21,
+        'HCLKDCS0_SEL':    22,
+        'HCLKDCS1_SEL':    23,
+        'DCC0':            24,
+        'DCC1':            25,
+        'DLYMUX':          26,
+        'HCLKDIV_DIV':     27,
+        'HCLKDIV_RST':     28,
+    }
+
+hclk_attrvals = {
+        'UNKNOWN':          0,
+        'DIVCIBRST2':       1,
+        'DIVCIBRST3':       2,
+        'DIV2':             3,
+        'DIVCIBRST0':       4, 
+        'DIVCIBRST1':       5,
+        'DIVCIBRST4':       6,
+        'DIVCIBRST5':       7,
+        'ENABLE':           8,
+        'BRGCIBSEL0':       9,
+        'BRGCIBSEL1':      10,
+        'BRGCIBSTOP0':     11,
+        'BRGCIBSTOP1':     12,
+        '2':               13,
+        '3.5':             14,
+        '4':               15,
+        '5':               16,
+        'HCLKCIBSTOP0':    17,
+        'HCLKCIBSTOP1':    18,
+        'HCLKCIBSTOP2':    19,
+        'HCLKCIBSTOP3':    20,
+        'HCLKBK10':        21,
+        'HCLKBK11':        22,
+        '8':               23,
+        'DIVCIBRST':       24,
+        'NEG_80':          25,
+        '80':              26,
+    }
+
+
 # iologic
 iologic_attrids = {
         'INMODE':                   0,

apycula/gowin_pack.py

@@ -185,7 +185,7 @@ def get_bits(init_data):
 def get_bels(data):
     later = []
     if is_himbaechel:
-        belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC|BSRAM|ALU|MULTALU18X18|MULTALU36X18|MULTADDALU18X18|MULT36X36|MULT18X18|MULT9X9|PADD18|PADD9|BANDGAP|DQCE|DCS)(\w*)")
+        belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC|CLKDIV2|CLKDIV|BSRAM|ALU|MULTALU18X18|MULTALU36X18|MULTADDALU18X18|MULT36X36|MULT18X18|MULT9X9|PADD18|PADD9|BANDGAP|DQCE|DCS)(\w*)")
     else:
         belre = re.compile(r"R(\d+)C(\d+)_(?:GSR|SLICE|IOB|MUX2_LUT5|MUX2_LUT6|MUX2_LUT7|MUX2_LUT8|ODDR|OSC[ZFHWO]?|BUFS|RAMW|rPLL|PLLVR|IOLOGIC)(\w*)")
 
@@ -1989,6 +1989,53 @@ def set_osc_attrs(db, typ, params):
         add_attr_val(db, 'OSC', fin_attrs, attrids.osc_attrids[attr], val)
     return fin_attrs
 
+def bin_str_to_dec(str_val):
+    bin_pattern = r'^[0,1]+'
+    bin_str = re.findall(bin_pattern, str_val)
+    if bin_str:
+        dec_num = int(bin_str[0], 2)
+        return str(dec_num)
+    return None
+
+
+
+_hclk_default_params ={"GSREN": "false", "DIV_MODE":"2"}
+def set_hclk_attrs(db, params, num, typ, cell_name):
+    name_pattern = r'^_HCLK([0,1])_SECT([0,1])$'
+    params = dict(params or _hclk_default_params)   
+    attrs = {}
+    pattern_match = re.findall(name_pattern, num)
+    if (not pattern_match):
+        raise Exception (f"Unknown HCLK Bel/HCLK Section: {typ}{num}")
+    hclk_idx, section_idx = pattern_match[0]
+
+    valid_div_modes = ["2", "3.5", "4", "5"]
+    if device in ["GW1N-1S","GW1N-2","GW1NR-2","GW1NS-4","GW1NS-4C","GW1NSR-4",\
+                       "GW1NSR-4C","GW1NSER-4C","GW1N-9","GW1NR-9", "GW1N-9C","GW1NR-9C","GW1N-1P5"]:
+        valid_div_modes.append("8")
+
+    if (params["DIV_MODE"]) not in valid_div_modes:
+        bin_match = bin_str_to_dec(params["DIV_MODE"])
+        if bin_match is None or bin_match not in valid_div_modes:
+            raise Exception(f"Invalid DIV_MODE {bin_match or params['DIV_MODE']} for CLKDIV {cell_name} on device {device}")
+        params["DIV_MODE"] = str(bin_match[0])
+
+
+    if (typ == "CLKDIV2"):
+        attrs[f"BK{section_idx}MUX{hclk_idx}_OUTSEL"] = "DIV2"
+    elif (typ == "CLKDIV"):
+        attrs[f"HCLKDIV{hclk_idx}_DIV"] = params["DIV_MODE"]         
+        if (section_idx == '1'):
+            attrs[f"HCLKDCS{hclk_idx}_SEL"] = f"HCLKBK{section_idx}{hclk_idx}"
+
+    fin_attrs = set()
+    for attr, val in attrs.items():
+        if isinstance(val, str):
+            val = attrids.hclk_attrvals[val]
+        add_attr_val(db, 'HCLK', fin_attrs, attrids.hclk_attrids[attr], val)
+    return fin_attrs
+
+
 _iologic_default_attrs = {
         'DUMMY': {},
         'IOLOGIC': {},
@@ -2054,7 +2101,8 @@ def set_iologic_attrs(db, attrs, param):
             in_attrs['ISI'] = 'ENABLE'
         in_attrs['LSRIMUX_0'] = '0'
         in_attrs['CLKOMUX'] = 'ENABLE'
-        #in_attrs['LSRMUX_LSR'] = 'INV'
+        # in_attrs['LSRMUX_LSR'] = 'INV'
+
     if 'INMODE' in attrs:
         if param['IOLOGIC_TYPE'] not in {'IDDR', 'IDDRC'}:
             #in_attrs['CLKODDRMUX_WRCLK'] = 'ECLK0'
@@ -2452,6 +2500,9 @@ def place(db, tilemap, bels, cst, args):
             cfg_tile = tilemap[(0, 37)]
             for r, c in bits:
                 cfg_tile[r][c] = 1
+        elif typ in ["CLKDIV", "CLKDIV2"]:
+            hclk_attrs = set_hclk_attrs(db, parms, num, typ, cellname)
+            bits = get_shortval_fuses(db, tiledata.ttyp, hclk_attrs, "HCLK")
         elif typ == 'DQCE':
             # Himbaechel only
             pipre = re.compile(r"X(\d+)Y(\d+)/([\w_]+)/([\w_]+)")

apycula/tiled_fuzzer.py

@@ -267,6 +267,8 @@ def fse_iob(fse, db, pin_locations, diff_cap_info, locations):
     chipdb.pll_pads(db, device, pad_locs)
 
     chipdb.dat_portmap(dat, db, device)
+    chipdb.add_hclk_bels(dat, db, device)
+
 
     # XXX GW1NR-9 has interesting IOBA pins on the bottom side
     if device == 'GW1N-9' :

apycula/wirenames.py

@@ -69,6 +69,19 @@
     101: 'BRPLL0CLK0', 102: 'BRPLL0CLK1', 103: 'BRPLL0CLK2', 104: 'BRPLL0CLK3',
 })
 clknames.update({n: f"UNK{n}" for n in range(105, 121)})
+# These are CLKDIV output nodes
+# clknames.update({
+#     106: 'THCLK0_CLKDIV_CLKOUT', 108:'THCLK1_CLKDIV_CLKOUT',
+#     118: 'RHCLK0_CLKDIV_CLKOUT', 120:'RHCLK1_CLKDIV_CLKOUT',
+#     110: 'BHCLK0_CLKDIV_CLKOUT', 112:'BHCLK1_CLKDIV_CLKOUT',
+#     114: 'LHCLK0_CLKDIV_CLKOUT', 116:'LHCLK1_CLKDIV_CLKOUT',
+# })
+clknames.update({
+    106: 'THCLK0CLKDIV', 108:'THCLK1CLKDIV',
+    118: 'RHCLK0CLKDIV', 120:'RHCLK1CLKDIV',
+    110: 'BHCLK0CLKDIV', 112:'BHCLK1CLKDIV',
+    114: 'LHCLK0CLKDIV', 116:'LHCLK1CLKDIV',
+})
 # These are the external clock pins, one on each side
 clknames.update({
     121: 'PCLKT0', 122: 'PCLKT1', 123: 'PCLKB0', 124: 'PCLKB1',
@@ -116,14 +129,20 @@
     2: 'HCLK_IN0', 3: 'HCLK_IN1', 4: 'HCLK_IN2', 5: 'HCLK_IN3'
 })
 
-# outputs
+# HCLK section inputs
 hclknames.update({
-    10: 'HCLK_OUT0', 11: 'HCLK_OUT1', 12: 'HCLK_OUT2', 13: 'HCLK_OUT3'
+    10: 'HCLK0_SECT0_IN', 11: 'HCLK0_SECT1_IN', 12: 'HCLK1_SECT0_IN', 13: 'HCLK1_SECT1_IN'
 })
-# these work as inputs in GW1N-9c
+
+# Bypass connections from HCLK_IN to HCLK_OUT
 hclknames.update({
     16: 'HCLK_9IN0', 17: 'HCLK_9IN1', 18: 'HCLK_9IN2', 19: 'HCLK_9IN3'
 })
 
+# CLKDIV2 CLKOUT spurs on the GW1N-9C
+hclknames.update({
+    20: 'HCLK_9_CLKDIV2_SECT0_OUT', 22:'HCLK_9_CLKDIV2_SECT2_OUT'
+})
+
 
 hclknumbers = {v: k for k, v in hclknames.items()}

doc/hclk.md

@@ -0,0 +1,12 @@
+# HCLK
+
+The High-speed CLocK tiles house the `CLKDIV` and `CLKDIV2` bels, among other functions. `CLKDIV` can drive `IOLOGIC`'s `FCLK` (via `HCLK_OUT`) but can also be used as a generic clock source. In contrast, the output of `CLKDIV2` can not be used as a generic clock source; however it can drive `CLKDIV`'s `HCLKIN`, `IOLOGIC`'s `FCLK`, and (per Gowin's documentation), PLLs.
+
+![Prototypical HCLK](fig/hclk.svg)
+
+
+The above diagram shows a prototypical HCLK. The GW1N-9C notably bucks this trend, having some wires repurposed, presumably to enable more direct connections by bypassing some fuses and muxes. It is also worthy of note that in the GW1N-9C, CLKDIV's CLKOUT cannot be connected directly to HCLK_OUT, and must thus take a roundtrip through the centre tiles.
+
+As a general rule, signals in one HCLK section are not allowd to connect to another HCLK section. As such, when the input to CLKDIV comes from one HCLK section, it's output must also go to the same section. For ease with following this rule in PnR, the current implementation of HCLK pretends that there are two `CLKDIVs` rather than one. The GW1N-9C once again breaks the norm, having special wires that connect the output of CLKDIV2 in the upper sections to HCLK_OUT in the lower sections.
+
+`HCLKMUX` (for sharing input signals between HCLKs) and `HCLKEN` are currently undocumented and unsupported ;).