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Deviation Between Yosys RTLIL EBNF Docs and RTLIL Lex/Yacc Frontend
pending-verification
This issue is pending verification and/or reproduction
#4811
opened Dec 10, 2024 by
ThePerfectComputer
Synthesis with -nowidelut gives drastically better results
pending-verification
This issue is pending verification and/or reproduction
#4798
opened Dec 5, 2024 by
t-wallet
techmap should warn when CONSTMSK/CONSTVAL are used with a nonexistent port
feature-request
#4795
opened Dec 3, 2024 by
Ravenslofty
Preservation of signedness flag on attribute values inconsistent
pending-verification
This issue is pending verification and/or reproduction
#4793
opened Dec 2, 2024 by
povik
read_verilog gives multiple drivers to variables initialized both in declaration and initial
pending-verification
This issue is pending verification and/or reproduction
#4792
opened Dec 2, 2024 by
widlarizer
cxxrtl
output port changes value after back to back .step()
bug
cxxrtl
#4786
opened Nov 29, 2024 by
rroohhh
read_verilog: array of instances parsing assertion failure
pending-verification
This issue is pending verification and/or reproduction
#4785
opened Nov 29, 2024 by
Muxianesty
Verilog: Mixing integer and real values causes error
pending-verification
This issue is pending verification and/or reproduction
#4780
opened Nov 28, 2024 by
flafflar
Docs issues for offline pdf builds
pending-verification
This issue is pending verification and/or reproduction
#4777
opened Nov 28, 2024 by
KrystalDelusion
Error: Abc_CommandAbc9If(): Mapping of GIA has failed.
pending-verification
This issue is pending verification and/or reproduction
#4766
opened Nov 24, 2024 by
spth
Measure global_id_index_ construction overhead
feature-request
#4761
opened Nov 20, 2024 by
widlarizer
Internal Yosys nodes not removed
pending-verification
This issue is pending verification and/or reproduction
#4738
opened Nov 13, 2024 by
ashkanr65
Module parameters are not affected by setundef pass
pending-verification
This issue is pending verification and/or reproduction
#4732
opened Nov 12, 2024 by
kamilrakoczy
muxcover generates x states
pending-verification
This issue is pending verification and/or reproduction
#4722
opened Nov 8, 2024 by
miradarya
Yosys does not accept module port lists with .port_identifier
pending-verification
This issue is pending verification and/or reproduction
#4708
opened Nov 5, 2024 by
ldoolitt
Yosys seems to be inconsistent with the original design.
pending-verification
This issue is pending verification and/or reproduction
#4695
opened Oct 31, 2024 by
smlz123
segfault in proc_dlatch when latch is driven by conflicting drivers
bug
#4692
opened Oct 30, 2024 by
gadfort
Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v"
pending-verification
This issue is pending verification and/or reproduction
#4687
opened Oct 28, 2024 by
1353369570
'synth_intel' command,synthesis result is wrong
pending-verification
This issue is pending verification and/or reproduction
#4673
opened Oct 17, 2024 by
CL-liao
Assert
flow.wire_comb_defs[it].size() == 1
in write_cxxrtl
bug
cxxrtl
#4664
opened Oct 14, 2024 by
rroohhh
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