(conan-io#12705) OpenBlas: Add arch target option

aborzunov · Oct 14, 2022 · cb4021f · cb4021f
1 parent 399efd2
commit cb4021f
Showing 1 changed file with 144 additions and 0 deletions.
diff --git a/recipes/openblas/all/conanfile.py b/recipes/openblas/all/conanfile.py
@@ -5,6 +5,141 @@
 
 required_conan_version = ">=1.43.0"
 
+# Copypasting here content of OpenBlas/TargetList.txt
+# https://github.com/xianyi/OpenBLAS/blob/develop/TargetList.txt
+# https://github.com/xianyi/OpenBLAS#normal-compile
+openblas_target_list = [
+        "None",
+
+        # 1.X86/X86_64
+        # a)Intel CPU:
+        "P2",
+        "KATMAI",
+        "COPPERMINE",
+        "NORTHWOOD",
+        "PRESCOTT",
+        "BANIAS",
+        "YONAH",
+        "CORE2",
+        "PENRYN",
+        "DUNNINGTON",
+        "NEHALEM",
+        "SANDYBRIDGE",
+        "HASWELL",
+        "SKYLAKEX",
+        "ATOM",
+        "COOPERLAKE",
+        "SAPPHIRERAPIDS",
+
+        # b)AMD CPU:
+        "ATHLON",
+        "OPTERON",
+        "OPTERON_SSE3",
+        "BARCELONA",
+        "SHANGHAI",
+        "ISTANBUL",
+        "BOBCAT",
+        "BULLDOZER",
+        "PILEDRIVER",
+        "STEAMROLLER",
+        "EXCAVATOR",
+        "ZEN",
+
+        # c)VIA CPU:
+        "SSE_GENERIC",
+        "VIAC3",
+        "NANO",
+
+        # 2.Power CPU:
+        "POWER4",
+        "POWER5",
+        "POWER6",
+        "POWER7",
+        "POWER8",
+        "POWER9",
+        "POWER10",
+        "PPCG4",
+        "PPC970",
+        "PPC970MP",
+        "PPC440",
+        "PPC440FP2",
+        "CELL",
+
+        # 3.MIPS CPU:
+        "P5600",
+        "MIPS1004K",
+        "MIPS24K",
+
+        # 4.MIPS64 CPU:
+        "MIPS64_GENERIC",
+        "SICORTEX",
+        "LOONGSON3A",
+        "LOONGSON3B",
+        "I6400",
+        "P6600",
+        "I6500",
+
+        # 5.IA64 CPU:
+        "ITANIUM2",
+
+        # 6.SPARC CPU:
+        "SPARC",
+        "SPARCV7",
+
+        # 7.ARM CPU:
+        "CORTEXA15",
+        "CORTEXA9",
+        "ARMV7",
+        "ARMV6",
+        "ARMV5",
+
+        # 8.ARM 64-bit CPU:
+        "ARMV8",
+        "CORTEXA53",
+        "CORTEXA57",
+        "CORTEXA72",
+        "CORTEXA73",
+        "CORTEXA510",
+        "CORTEXA710",
+        "CORTEXX1",
+        "CORTEXX2",
+        "NEOVERSEN1",
+        "NEOVERSEV1",
+        "NEOVERSEN2",
+        "CORTEXA55",
+        "EMAG8180",
+        "FALKOR",
+        "THUNDERX",
+        "THUNDERX2T99",
+        "TSV110",
+        "THUNDERX3T110",
+        "VORTEX",
+        "A64FX",
+        "ARMV8SVE",
+        "FT2000",
+
+        # 9.System Z:
+        "ZARCH_GENERIC",
+        "Z13",
+        "Z14",
+
+        # 10.RISC-V 64:
+        "RISCV64_GENERIC",
+        "C910V",
+
+        # 11.LOONGARCH64:
+        "LOONGSONGENERIC",
+        "LOONGSON3R5",
+        "LOONGSON2K1000",
+
+        # 12. Elbrus E2000:
+        "E2K",
+
+        # 13. Alpha
+        "EV4",
+        "EV5",
+        "EV6",
+    ]
 
 class OpenblasConan(ConanFile):
     name = "openblas"
@@ -20,6 +155,7 @@ class OpenblasConan(ConanFile):
         "build_lapack": [True, False],
         "use_thread": [True, False],
         "dynamic_arch": [True, False],
+        "target": openblas_target_list,
     }
     default_options = {
         "shared": False,
@@ -72,6 +208,14 @@ def _configure_cmake(self):
         cmake.definitions["DYNAMIC_ARCH"] = self.options.dynamic_arch
         cmake.definitions["USE_THREAD"] = self.options.use_thread
 
+        if self.options.target != "None":
+            cmake.definitions["TARGET"] = self.options.target
+            self.output.info(
+                    f"Setting target arch to {self.options.target} and "
+                    "passing this as value to TARGET variable of openblas cmake. "
+                    "For more information, check out "
+                    "https://github.com/xianyi/OpenBLAS#normal-compile")
+
         # Required for safe concurrent calls to OpenBLAS routines
         cmake.definitions["USE_LOCKING"] = not self.options.use_thread