Fix 16-bit x86_pextr encoding

The x86 ISA has (at least) two encodings for PEXTRW: 1. in the SSE2 opcode (66 0f c5) the XMM operand uses r/m and the GPR operand uses reg 2. in the SSE4.1 opcode (66 0f 3a 15) the XMM operand uses reg and the GPR operand uses r/m This changes the 16-bit x86_pextr encoding from #1 to #2 to match the other PEXTR* implementations (all #2 style).
abrown · Sep 18, 2019 · c33cb52 · c33cb52
1 parent 4ab3939
commit c33cb52
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/cranelift-codegen/meta/src/isa/x86/encodings.rs b/cranelift-codegen/meta/src/isa/x86/encodings.rs
@@ -1874,8 +1874,8 @@ pub(crate) fn define(
     // SIMD extractlane
     for (lane_bits, opcode, isap) in [
         (8, vec![0x66, 0x0f, 0x3a, 0x14], Some(use_sse41_simd)), // PEXTRB
-        (16, vec![0x66, 0x0f, 0xc5], None), // PEXTRW from SSE2, SSE4.1 has a PEXTRW that can
-        // move to reg/m16 but the opcode is four bytes
+        (16, vec![0x66, 0x0f, 0x3a, 0x15], Some(use_sse41_simd)), // PEXTRW from SSE4.1, SSE2 has a
+        // PEXTRW that can move to reg/m16 but the ModR/M assignment is backwards
         (32, vec![0x66, 0x0f, 0x3a, 0x16], Some(use_sse41_simd)), // PEXTRD
         (64, vec![0x66, 0x0f, 0x3a, 0x16], Some(use_sse41_simd)), // PEXTRQ, only x86_64
     ]

diff --git a/filetests/isa/x86/extractlane-binemit.clif b/filetests/isa/x86/extractlane-binemit.clif
@@ -17,7 +17,7 @@ function %test_extractlane_i16() {
 ebb0:
 [-, %rax]   v0 = iconst.i16 4
 [-, %xmm1]  v1 = splat.i16x8 v0
-[-, %rax]   v2 = x86_pextr v1, 4    ; bin: 66 0f c5 c8 04
+[-, %rax]   v2 = x86_pextr v1, 4    ; bin: 66 0f 3a 15 c8 04
             return
 }