Merge branch 'main' into fix/create_volume_plot

.github/workflows/ci_cd.yml

@@ -115,8 +115,8 @@ jobs:
         run: |
           python doc/print_errors.py
 
-      - name: Upload HTML documentation without  artifact
-        uses: actions/upload-artifact@v3
+      - name: Upload HTML documentation
+        uses: actions/upload-artifact@v4
         with:
           name: documentation-html
           path: doc/_build/html
@@ -127,7 +127,7 @@ jobs:
           make -C doc pdf
 
       - name: Upload PDF documentation
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: documentation-pdf
           path: doc/_build/latex/PyAEDT-Documentation-*.pdf
@@ -187,9 +187,9 @@ jobs:
           flags: system,solver
 
       - name: Upload pytest test results
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
-          name: pytest-solver-results
+          name: pytest-solver-windows
           path: junit/test-results.xml
         if: ${{ always() }}
 
@@ -245,9 +245,9 @@ jobs:
           flags: system,solver
 
       - name: Upload pytest test results
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
-          name: pytest-solver-results
+          name: pytest-solver-linux
           path: junit/test-results.xml
         if: ${{ always() }}
 
@@ -310,9 +310,9 @@ jobs:
           flags: system
 
       - name: Upload pytest test results
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
-          name: pytest-results
+          name: pytest-windows
           path: junit/test-results.xml
         if: ${{ always() }}
 
@@ -380,9 +380,9 @@ jobs:
           flags: system,solver
 
       - name: Upload pytest test results
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
-          name: pytest-solver-results
+          name: pytest-linux
           path: junit/test-results.xml
         if: ${{ always() }}
 

.pre-commit-config.yaml

@@ -12,7 +12,7 @@ exclude: |
 
 repos:
 - repo: https://github.com/psf/black
-  rev: 24.8.0  # IF VERSION CHANGES --> MODIFY "blacken-docs" MANUALLY AS WELL!!
+  rev: 24.10.0  # IF VERSION CHANGES --> MODIFY "blacken-docs" MANUALLY AS WELL!!
   hooks:
   - id: black
     args:
@@ -41,7 +41,7 @@ repos:
       - tomli
 
 - repo: https://github.com/pre-commit/pre-commit-hooks
-  rev: v4.6.0
+  rev: v5.0.0
   hooks:
   - id: debug-statements
   - id: trailing-whitespace
@@ -53,10 +53,10 @@ repos:
     - id: check-github-workflows
 
 - repo: https://github.com/asottile/blacken-docs
-  rev: 1.18.0
+  rev: 1.19.0
   hooks:
   -   id: blacken-docs
-      additional_dependencies: [black==24.8.0]
+      additional_dependencies: [black==24.10.0]
 
 # This validates our pre-commit.ci configuration
 - repo: https://github.com/pre-commit-ci/pre-commit-ci-config

_unittest/test_01_3dlayout_edb.py

@@ -282,8 +282,9 @@ def test_08_merge(self, add_app):
             assert (comp.location[1] - 0.2) < tol
 
     def test_10_change_stackup(self):
-        assert self.aedtapp.modeler.layers.change_stackup_type("Multizone", 4)
-        assert len(self.aedtapp.modeler.layers.zones) == 3
+        if config["NonGraphical"]:
+            assert self.aedtapp.modeler.layers.change_stackup_type("Multizone", 4)
+            assert len(self.aedtapp.modeler.layers.zones) == 3
         assert self.aedtapp.modeler.layers.change_stackup_type("Overlap")
         assert self.aedtapp.modeler.layers.change_stackup_type("Laminate")
         assert not self.aedtapp.modeler.layers.change_stackup_type("lami")

_unittest/test_01_Design.py

@@ -176,7 +176,7 @@ def test_12_variables(self):
         assert "test" not in self.aedtapp.variable_manager.variables
 
     def test_13_designs(self):
-        assert self.aedtapp._insert_design("HFSS", design_name="TestTransient") == "TestTransient"
+        assert self.aedtapp._insert_design(design_name="TestTransient", design_type="HFSS") == "TestTransient"
         self.aedtapp.delete_design("TestTransient")
         self.aedtapp.insert_design("NewDesign")
 

_unittest/test_12_PostProcessing.py

@@ -56,10 +56,17 @@
     m2d_file = "m2d_field_lines_test"
 
 test_circuit_name = "Switching_Speed_FET_And_Diode"
-test_emi_name = "EMI_RCV_241"
+if config["desktopVersion"] > "2024.2":
+    test_emi_name = "EMI_RCV_251"
+else:
+    test_emi_name = "EMI_RCV_241"
+
 eye_diagram = "SimpleChannel"
 ami = "ami"
-ipk_post_proj = "for_icepak_post"
+if config["desktopVersion"] > "2024.2":
+    ipk_post_proj = "for_icepak_post_parasolid"
+else:
+    ipk_post_proj = "for_icepak_post"
 test_subfolder = "T12"
 settings.enable_pandas_output = True
 

_unittest/test_20_HFSS.py

@@ -676,8 +676,14 @@ def test_12_create_perfects_on_objects(self):
         self.aedtapp.insert_design("test_12")
         box1 = self.aedtapp.modeler.create_box([0, 0, 0], [10, 10, 5], "perfect1", "Copper")
         box2 = self.aedtapp.modeler.create_box([0, 0, 10], [10, 10, 5], "perfect2", "copper")
-        pe = self.aedtapp.create_perfecth_from_objects("perfect1", "perfect2", self.aedtapp.AxisDir.ZPos)
-        ph = self.aedtapp.create_perfecte_from_objects("perfect1", "perfect2", self.aedtapp.AxisDir.ZNeg)
+
+        ph = self.aedtapp.create_perfecth_from_objects(
+            box1.name, box2.name, self.aedtapp.AxisDir.ZNeg, is_boundary_on_plane=False
+        )
+
+        pe = self.aedtapp.create_perfecte_from_objects(
+            box1.name, box2.name, self.aedtapp.AxisDir.ZNeg, is_boundary_on_plane=False
+        )
         assert pe.name in self.aedtapp.modeler.get_boundaries_name()
         assert pe.update()
         assert ph.name in self.aedtapp.modeler.get_boundaries_name()
@@ -978,8 +984,8 @@ def test_34_object_material_properties(self):
         assert props
 
     def test_35_set_export_touchstone(self):
-        assert self.aedtapp.set_export_touchstone(True)
-        assert self.aedtapp.set_export_touchstone(False)
+        assert self.aedtapp.export_touchstone_on_completion(True)
+        assert self.aedtapp.export_touchstone_on_completion(False)
 
     def test_36_assign_radiation_to_objects(self):
         self.aedtapp.modeler.create_box([-100, -100, -100], [200, 200, 200], name="Rad_box")
@@ -1567,12 +1573,15 @@ def test_65_component_array(self, add_app):
         array.cells[0][1].component = array.component_names[3]
         assert array.cells[0][1].component == array.component_names[3]
 
-        hfss_array.component_array["A1"].name = "Array_new"
-        assert hfss_array.component_array_names[0] == "Array_new"
-        hfss_array.component_array["Array_new"].name = "A1"
+        name = "Array_new"
+        hfss_array.component_array["A1"].name = name
+        assert hfss_array.component_array_names[0] == name
 
+        if config["desktopVersion"] < "2025.1":
+            name = "A1"
+            hfss_array.component_array["Array_new"].name = name
         omodel = hfss_array.get_oo_object(hfss_array.odesign, "Model")
-        oarray = hfss_array.get_oo_object(omodel, "A1")
+        oarray = hfss_array.get_oo_object(omodel, name)
 
         assert array.visible
         array.visible = False
@@ -1708,4 +1717,4 @@ def test_70_export_on_completion(self, add_app, local_scratch):
         aedtapp = add_app(project_name="test_70")
         assert aedtapp.export_touchstone_on_completion()
         assert aedtapp.export_touchstone_on_completion(export=True, output_dir=self.local_scratch.path)
-        assert aedtapp.set_export_touchstone()
+        assert aedtapp.export_touchstone_on_completion()

_unittest/test_41_3dlayout_modeler.py

@@ -588,8 +588,9 @@ def test_21_variables(self):
         assert isinstance(self.aedtapp.available_variations.nominal_w_values, list)
 
     def test_26_duplicate(self):
-        assert self.aedtapp.modeler.duplicate("myrectangle", 2, [1, 1])
-        assert self.aedtapp.modeler.duplicate_across_layers("mycircle2", "Bottom")
+        n2 = self.aedtapp.modeler.create_rectangle("Top", [0, 0], [6, 8], 3, 2, "myrectangle_d")
+        assert self.aedtapp.modeler.duplicate("myrectangle_d", 2, [1, 1])
+        assert self.aedtapp.modeler.duplicate_across_layers("myrectangle_d", "Bottom")
 
     def test_27_create_pin_port(self):
         port = self.aedtapp.create_pin_port("PinPort1")

_unittest/test_45_FilterSolutions/resources/library_parts_test.cfg

@@ -0,0 +1,45 @@
+modsubType=2
+modsubEr=2.25
+modsubRho=4.2E+07
+modsubTand=0.065
+modsubH=0.003
+modsubT=3.5E-07
+modsubS=0.00127
+modsubC=0.00635
+modsubErsel=-1
+modsubRhosel=-1
+modsubTandsel=-1
+modsubTanddef=0
+modsubiSubSel=0
+modsubName=User Defined Substrate
+modsubBrow=
+modsubNameVal=2.25
+modAnsSubIndex=0
+modAWRSubIndex=0
+webAWRSubIndex=0
+locAWRSubIndex=0
+ModelData=2
+ModelDataV=1
+ModelInd=0
+ModelCap=0
+ModelRes=0
+ModelIndV=1
+ModelCapV=1
+ModelResV=1
+modRatLen=2
+modRatZ=1
+Interc=1
+modActLen=0.00254
+modActWid=0.00127
+modRatZMin=0.5
+modRatZMax=2
+modRatLenMin=0.5
+modRatLenMax=2
+modActLenMin=0.00127
+modActWidMin=0.000635
+modActLenMax=0.00508
+modActWidMax=0.00254
+useGeo=0
+OptGeo=1
+indTol=1
+capTol=1

_unittest/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py

@@ -90,3 +90,19 @@ def test_remove_row(self):
             info.value.args[0]
             == "Either no value is set for this band or the rowIndex must be greater than zero and less than row count"
         )
+
+    def test_clear_table(self):
+        design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
+        design.attributes.filter_multiple_bands_enabled = True
+        # There are 2 rows in the table by default
+        assert design.multiple_bands_table.row_count == 2
+        design.multiple_bands_table.clear_table()
+        assert design.multiple_bands_table.row_count == 0
+        # Check if the table is empty for all 7 rows
+        for i in range(7):
+            with pytest.raises(RuntimeError) as info:
+                design.multiple_bands_table.row(i)
+            assert (
+                info.value.args[0] == "Either no value is set for this band or the rowIndex must be greater than "
+                "zero and less than row count"
+            )

_unittest/test_45_FilterSolutions/test_filter/test_transmission_zeros.py

@@ -69,13 +69,13 @@ def test_append_row(self):
         assert info.value.args[0] == self.input_value_blank_msg
         design.transmission_zeros_bandwidth.append_row("1600M")
         assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "")
-        design.transmission_zeros_bandwidth.clear_row()
+        design.transmission_zeros_bandwidth.clear_table()
         design.transmission_zeros_bandwidth.append_row(zero="1600M", position="2")
         assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2")
-        design.transmission_zeros_bandwidth.clear_row()
+        design.transmission_zeros_bandwidth.clear_table()
         design.transmission_zeros_ratio.append_row("1.6")
         assert design.transmission_zeros_ratio.row(0) == ("1.6", "")
-        design.transmission_zeros_ratio.clear_row()
+        design.transmission_zeros_ratio.clear_table()
         design.transmission_zeros_ratio.append_row(zero="1.6", position="2")
         assert design.transmission_zeros_ratio.row(0) == ("1.6", "2")
 
@@ -97,7 +97,7 @@ def test_insert_row(self):
         assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "")
         design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2")
         assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2")
-        design.transmission_zeros_bandwidth.clear_row()
+        design.transmission_zeros_bandwidth.clear_table()
         design.transmission_zeros_ratio.insert_row(0, "1.6")
         assert design.transmission_zeros_ratio.row(0) == ("1.6", "")
         design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2")
@@ -114,17 +114,17 @@ def test_remove_row(self):
             design.transmission_zeros_bandwidth.row(0)
         assert info.value.args[0] == self.no_transmission_zero_msg
 
-    def test_clear_row(self):
+    def test_clear_table(self):
         design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2")
         assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2")
-        design.transmission_zeros_bandwidth.clear_row()
+        design.transmission_zeros_bandwidth.clear_table()
         with pytest.raises(RuntimeError) as info:
             design.transmission_zeros_bandwidth.row(0)
         assert info.value.args[0] == self.no_transmission_zero_msg
         design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2")
         assert design.transmission_zeros_ratio.row(0) == ("1.6", "2")
-        design.transmission_zeros_ratio.clear_row()
+        design.transmission_zeros_ratio.clear_table()
         with pytest.raises(RuntimeError) as info:
             design.transmission_zeros_ratio.row(0)
         assert info.value.args[0] == self.no_transmission_zero_msg

_unittest/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py

@@ -45,7 +45,7 @@
 
 
 @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.")
-@pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1")
+@pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2")
 class TestClass:
     def test_modelithics_inductor_list_count(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)

_unittest/test_launch_desktop.py

@@ -90,7 +90,7 @@ def test_run_desktop_maxwell2d(self):
         assert aedtapp.solution_type == "Magnetostatic"
 
     def test_run_desktop_hfss(self):
-        aedtapp = Hfss()
+        aedtapp = Hfss(solution_type="Terminal")
         assert aedtapp.design_type == "HFSS"
         assert "Terminal" in aedtapp.solution_type
 
@@ -103,3 +103,10 @@ def test_run_desktop_circuit_netlist(self):
         aedtapp = CircuitNetlist()
         assert aedtapp.design_type == "Circuit Netlist"
         assert aedtapp.solution_type == ""
+
+    def test_run_desktop_settings(self):
+        aedtapp = Hfss()
+        assert aedtapp.desktop_class.disable_optimetrics()
+        assert aedtapp.get_registry_key_int("Desktop/Settings/ProjectOptions/EnableLegacyOptimetricsTools") == 0
+        assert aedtapp.desktop_class.enable_optimetrics()
+        assert aedtapp.get_registry_key_int("Desktop/Settings/ProjectOptions/EnableLegacyOptimetricsTools") == 1

_unittest_solvers/test_00_analyze.py

@@ -23,7 +23,7 @@
 original_project_name = "ANSYS-HSD_V1"
 transient = "Transient_StrandedWindings"
 
-if config["desktopVersion"] > "2022.2":
+if desktop_version > "2022.2":
     component = "Circ_Patch_5GHz_232.a3dcomp"
 else:
     component = "Circ_Patch_5GHz.a3dcomp"
@@ -162,7 +162,7 @@ def test_02_hfss_export_results(self, hfss_app):
         hfss_app.insert_design("Array_simple_resuts", "Modal")
         from ansys.aedt.core.generic.general_methods import read_json
 
-        if config["desktopVersion"] > "2023.1":
+        if desktop_version > "2023.1":
             dict_in = read_json(os.path.join(local_path, "example_models", test_subfolder, "array_simple_232.json"))
             dict_in["Circ_Patch_5GHz_232_1"] = os.path.join(local_path, "example_models", test_subfolder, component)
             dict_in["cells"][(3, 3)] = {"name": "Circ_Patch_5GHz_232_1"}
@@ -349,6 +349,10 @@ def test_04a_3dl_generate_mesh(self):
     def test_04b_3dl_analyze_setup(self):
         assert self.hfss3dl_solve.export_touchstone_on_completion(export=False)
         assert self.hfss3dl_solve.export_touchstone_on_completion(export=True)
+        if desktop_version > "2024.2":
+            assert self.hfss3dl_solve.set_export_touchstone()
+        else:
+            assert not self.hfss3dl_solve.set_export_touchstone()
         assert self.hfss3dl_solve.analyze_setup("Setup1", cores=4, blocking=False)
         assert self.hfss3dl_solve.are_there_simulations_running
         assert self.hfss3dl_solve.stop_simulations()
@@ -377,8 +381,10 @@ def test_04e_3dl_export_results(self):
         assert len(files) > 0
 
     def test_04f_3dl_set_export_touchstone(self):
-        assert self.hfss3dl_solve.set_export_touchstone(True)
-        assert self.hfss3dl_solve.set_export_touchstone(False)
+        assert self.hfss3dl_solve.export_touchstone_on_completion(True)
+        assert self.hfss3dl_solve.export_touchstone_on_completion(False)
+        if desktop_version > "2024.2":
+            assert self.hfss3dl_solve.set_export_touchstone()
 
     def test_04g_3dl_get_all_sparameter_list(self):
         assert self.hfss3dl_solve.get_all_sparameter_list == ["S(Port1,Port1)", "S(Port1,Port2)", "S(Port2,Port2)"]