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FIX: Extend ref pin search outside component with create port on comp…
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…onent (#650)

* hfsspi SimsetupInfo bug fixed

* temp

* SimulationConfiguration class crate port on component with no ref pins fixed

* SimulationConfiguration class crate port on component with no ref pins fixed

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

* MISC: Auto fixes from pre-commit.com hooks

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* SimulationConfiguration class crate port on component with no ref pins fixed

* SimulationConfiguration class crate port on component with no ref pins fixed

* SimulationConfiguration class crate port on component with no ref pins fixed

* Update src/pyedb/dotnet/edb_core/components.py

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>

---------

Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com>
Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
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@svandenb-dev @SMoraisAnsys @pre-commit-ci
3 people authored Jul 9, 2024
1 parent 791c7a6 commit 98c238a
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Showing 4 changed files with 105 additions and 18 deletions.
92 changes: 74 additions & 18 deletions src/pyedb/dotnet/edb_core/components.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -766,20 +766,44 @@ def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0, port
>>> edb.close_edb()
"""

if isinstance(pins, str) or isinstance(pins, EDBPadstackInstance):
if isinstance(pins, str):
pins = [pins]
elif isinstance(pins, EDBPadstackInstance):
pins = [pins.name]
if isinstance(reference_pins, str):
reference_pins = [reference_pins]
if isinstance(refdes, str) or isinstance(refdes, EDBComponent):
if isinstance(reference_pins, list):
_temp = []
for ref_pin in reference_pins:
if isinstance(ref_pin, int):
if ref_pin in self._padstack.instances:
_temp.append(self._padstack.instances[ref_pin])
elif isinstance(ref_pin, str):
if ref_pin in self.instances[refdes].pins:
_temp.append(self.instances[refdes].pins[ref_pin])
else:
p = [pp for pp in list(self._padstack.instances.values()) if pp.name == ref_pin]
if p:
_temp.append(p)
elif isinstance(ref_pin, EDBPadstackInstance):
_temp.append(ref_pin.name)
reference_pins = _temp
elif isinstance(reference_pins, int):
if reference_pins in self._padstack.instances:
reference_pins = self._padstack.instances[reference_pins]
if isinstance(refdes, str):
refdes = self.instances[refdes]
elif isinstance(refdes, self._pedb._edb.Cell.Hierarchy.Component):
refdes = EDBComponent(self._pedb, refdes)
refdes_pins = refdes.pins
if any(refdes.rlc_values):
return self.deactivate_rlc_component(component=refdes, create_circuit_port=True)
if len([pin for pin in pins if isinstance(pin, str)]) == len(pins):
cmp_pins = []
for pin_name in pins:
cmp_pin = [pin for pin in list(refdes.pins.values()) if pin_name == pin.name]
cmp_pin = [pin for pin in list(refdes_pins.values()) if pin_name == pin.name]
if not cmp_pin:
cmp_pin = [pin for pin in list(refdes.pins.values()) if pin_name == pin.name.split("-")[1]]
cmp_pin = [pin for pin in list(refdes_pins.values()) if pin_name == pin.name.split("-")[1]]
if cmp_pin:
cmp_pins.append(cmp_pin[0])
if not cmp_pins:
Expand All @@ -793,15 +817,15 @@ def create_port_on_pins(self, refdes, pins, reference_pins, impedance=50.0, port
if len([pin for pin in reference_pins if isinstance(pin, str)]) == len(reference_pins):
ref_cmp_pins = []
for ref_pin_name in reference_pins:
cmp_ref_pin = [pin for pin in list(refdes.pins.values()) if ref_pin_name == pin.name]
if not cmp_ref_pin:
cmp_ref_pin = [pin for pin in list(refdes.pins.values()) if ref_pin_name == pin.name.split("-")[1]]
if cmp_ref_pin:
ref_cmp_pins.append(cmp_ref_pin[0])
if ref_pin_name in refdes_pins:
ref_cmp_pins.append(refdes_pins[ref_pin_name])
elif "-" in ref_pin_name and ref_pin_name.split("-")[1] in refdes_pins:
ref_cmp_pins.append(refdes_pins[ref_pin_name.split("-")[1]])
if not ref_cmp_pins:
return
reference_pins = ref_cmp_pins
if not len([pin for pin in reference_pins if isinstance(pin, EDBPadstackInstance)]) == len(reference_pins):
if not reference_pins:
self._logger.error("No reference pins found.")
return
if len(pins) > 1:
pec_boundary = False
Expand Down Expand Up @@ -883,7 +907,7 @@ def create_port_on_component(
solder_balls_size : float, optional
Solder balls diameter. When provided auto evaluation based on padstack size will be disabled.
solder_balls_mid_size : float, optional
Solder balls mid diameter. When provided if value is different than solder balls size, spheroid shape will
Solder balls mid-diameter. When provided if value is different than solder balls size, spheroid shape will
be switched.
Returns
Expand All @@ -904,11 +928,11 @@ def create_port_on_component(
if isinstance(component, str):
component = self.instances[component].edbcomponent
if not solder_balls_height:
solder_balls_height = self.components[component.GetName()].solder_ball_height
solder_balls_height = self.instances[component.GetName()].solder_ball_height
if not solder_balls_size:
solder_balls_size = self.components[component.GetName()].solder_ball_diameter[0]
solder_balls_size = self.instances[component.GetName()].solder_ball_diameter[0]
if not solder_balls_mid_size:
solder_balls_mid_size = self.components[component.GetName()].solder_ball_diameter[1]
solder_balls_mid_size = self.instances[component.GetName()].solder_ball_diameter[1]
if not isinstance(net_list, list):
net_list = [net_list]
for net in net_list:
Expand All @@ -934,6 +958,18 @@ def create_port_on_component(
return False
pin_layers = cmp_pins[0].GetPadstackDef().GetData().GetLayerNames()
if port_type == SourceType.CoaxPort:
ref_pins = [
p
for p in list(component.LayoutObjs)
if int(p.GetObjType()) == 1 and p.GetNet().GetName() in reference_net
]
if not ref_pins:
self._logger.error(
"No reference pins found on component. You might consider"
"using Circuit port instead since reference pins can be extended"
"outside the component automatically when not found."
)
return False
pad_params = self._padstack.get_pad_parameters(pin=cmp_pins[0], layername=pin_layers[0], pad_type=0)
if not pad_params[0] == 7:
if not solder_balls_size: # pragma no cover
Expand Down Expand Up @@ -981,17 +1017,25 @@ def create_port_on_component(
for p in ref_pins:
if not p.IsLayoutPin():
p.SetIsLayoutPin(True)
if len(ref_pins) == 0:
self._logger.info("No reference pin found on component {}.".format(component.GetName()))
if not ref_pins:
self._logger.warning("No reference pins found on component, the closest pin will be selected.")
do_pingroup = False
if do_pingroup:
if len(ref_pins) == 1:
ref_pins.is_pin = True
ref_pin_group_term = self._create_terminal(ref_pins[0])
else:
for pin in ref_pins:
pin.is_pin = True
ref_pin_group = self.create_pingroup_from_pins(ref_pins)
if not ref_pin_group:
self._logger.error(f"Failed to create reference pin group on component {component.GetName()}.")
return False
ref_pin_group_term = self._create_pin_group_terminal(ref_pin_group, isref=True)
ref_pin_group_term = self._create_pin_group_terminal(ref_pin_group, isref=False)
if not ref_pin_group_term:
self._logger.error(
f"Failed to create reference pin group terminal on component {component.GetName()}"
)
return False
for net in net_list:
pins = [pin for pin in cmp_pins if pin.GetNet().GetName() == net]
Expand All @@ -1013,7 +1057,19 @@ def create_port_on_component(
for net in net_list:
pins = [pin for pin in cmp_pins if pin.GetNet().GetName() == net]
for pin in pins:
self.create_port_on_pins(component, pin, ref_pins)
if ref_pins:
self.create_port_on_pins(component, pin, ref_pins)
else:
_pin = EDBPadstackInstance(pin, self._pedb)
ref_pin = _pin.get_reference_pins(
reference_net=reference_net[0], max_limit=1, component_only=False, search_radius=3e-3
)
if ref_pin:
self.create_port_on_pins(
component,
[EDBPadstackInstance(pin, self._pedb).name],
[EDBPadstackInstance(ref_pin[0], self._pedb).id],
)
return True

def _create_terminal(self, pin, term_name=None):
Expand Down
Binary file added tests/example_models/TEDB/component_no_ref_pins.aedb/edb.def
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4 changes: 4 additions & 0 deletions tests/legacy/system/conftest.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,6 +96,10 @@ def get_multizone_pcb(self):
aedb = self._copy_file_folder_into_local_folder("multi_zone_project.aedb")
return Edb(aedb, edbversion=desktop_version)

def get_no_ref_pins_component(self):
aedb = self._copy_file_folder_into_local_folder("TEDB/component_no_ref_pins.aedb")
return Edb(aedb, edbversion=desktop_version)


@pytest.fixture(scope="module")
def add_legacy_edb(local_scratch):
Expand Down
27 changes: 27 additions & 0 deletions tests/legacy/system/test_edb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1923,3 +1923,30 @@ def test_workflow(self, edb_examples):
edbapp.workflow.export_bill_of_materials(path_bom)
assert path_bom.exists()
edbapp.close()

def test_create_port_ob_component_no_ref_pins_in_component(self, edb_examples):
edbapp = edb_examples.get_no_ref_pins_component()
sim_setup = edbapp.new_simulation_configuration()
sim_setup.signal_nets = [
"net1",
"net2",
"net3",
"net4",
"net5",
"net6",
"net7",
"net8",
"net9",
"net10",
"net11",
"net12",
"net13",
"net14",
"net15",
]
sim_setup.power_nets = ["GND"]
sim_setup.solver_type = 7
sim_setup.components = ["J2E2"]
sim_setup.do_cutout_subdesign = False
edbapp.build_simulation_project(sim_setup)
assert len(edbapp.ports) == 15

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