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[SOL] Revamp peephole pass for explicit sign extension #119

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merged 1 commit into from
Dec 14, 2024

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@LucasSte LucasSte commented Dec 13, 2024

PR #116 commented out the peephole pass that used to remove unnecessary sign extensions when the ALU32 target feature was enabled. This PR revamps the implementation to remove redundant MOV64 that serves as zero extension.

The reason this works is the following:

  1. Every ALU32 instructions, except for mov32 reg, reg, zero extends values. This also includes mov32 reg, imm
  2. Truncating from a 64-bit register will always require a bit mask.
  3. We don't emit mov32 reg, reg for copying 32-bit values.
  4. It is safe to assume that every value in a 32-bit register is always zero extended, so the MOV64 is unnecessary (it only acts as a copy).

@LucasSte LucasSte requested a review from dmakarov December 14, 2024 09:27
@LucasSte LucasSte marked this pull request as ready for review December 14, 2024 09:27
@LucasSte LucasSte merged commit b70bb3f into anza-xyz:solana-rustc/18.1-2024-05-19 Dec 14, 2024
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@LucasSte LucasSte deleted the peep-1 branch December 14, 2024 15:26
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