Update memory_addr, use memory_addr::MemoryAddr to bound `PagingM…

…etaData::VirtAddr` (#6), and bump to v0.4.0 * update `memory_addr`, use `memory_addr::MemoryAddr` to bound `PagingMetaData::VirtAddr` * update `memory_addr` to (yet to publish) v0.3 * formatted * bump to 0.4.0-dev, to be discussed * remove temporary patch * add change log * bump to 0.4.0
arceos-org · Aug 27, 2024 · 2193fa5 · 2193fa5
1 parent 9048532
commit 2193fa5
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,11 @@
 # Changelog
 
+## 0.4.0
+
+### Breaking Changes
+
+- Update `memory_addr` to `0.3.0`, which is not backward compatible with `0.2.0`.
+
 ## 0.3.3
 
 - Support the use of `page_table_entry` at the ARM EL2 privilege level (via the `arm-el2` feature).

diff --git a/Cargo.toml b/Cargo.toml
@@ -7,7 +7,7 @@ members = [
 ]
 
 [workspace.package]
-version = "0.3.3"
+version = "0.4.0"
 authors = ["Yuekai Jia <equation618@gmail.com>"]
 license = "GPL-3.0-or-later OR Apache-2.0 OR MulanPSL-2.0"
 homepage = "https://github.com/arceos-org/arceos"

diff --git a/page_table_entry/Cargo.toml b/page_table_entry/Cargo.toml
@@ -16,7 +16,7 @@ arm-el2 = []
 
 [dependencies]
 bitflags = "2.6"
-memory_addr = "0.2"
+memory_addr = "0.3"
 
 [target.'cfg(any(target_arch = "aarch64", doc))'.dependencies]
 aarch64-cpu = "9.4"

diff --git a/page_table_multiarch/Cargo.toml b/page_table_multiarch/Cargo.toml
@@ -13,8 +13,8 @@ categories.workspace = true
 
 [dependencies]
 log = "0.4"
-memory_addr = "0.2"
-page_table_entry = { path = "../page_table_entry", version = "0.3" }
+memory_addr = "0.3"
+page_table_entry = { path = "../page_table_entry", version = "0.4.0" }
 
 [target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
 x86 = "0.52"

diff --git a/page_table_multiarch/README.md b/page_table_multiarch/README.md
@@ -30,7 +30,7 @@ Currently supported architectures and page table structures:
 ## Examples (x86_64)
 
 ```rust
-use memory_addr::{PhysAddr, VirtAddr};
+use memory_addr::{MemoryAddr, PhysAddr, VirtAddr};
 use page_table_multiarch::x86_64::{X64PageTable};
 use page_table_multiarch::{MappingFlags, PagingHandler, PageSize};
 

diff --git a/page_table_multiarch/src/bits64.rs b/page_table_multiarch/src/bits64.rs
@@ -3,7 +3,7 @@ extern crate alloc;
 use crate::{GenericPTE, PagingHandler, PagingMetaData};
 use crate::{MappingFlags, PageSize, PagingError, PagingResult, TlbFlush, TlbFlushAll};
 use core::marker::PhantomData;
-use memory_addr::{PhysAddr, PAGE_SIZE_4K};
+use memory_addr::{MemoryAddr, PhysAddr, PAGE_SIZE_4K};
 
 const ENTRY_COUNT: usize = 512;
 
@@ -139,7 +139,7 @@ impl<M: PagingMetaData, PTE: GenericPTE, H: PagingHandler> PageTable64<M, PTE, H
             return Err(PagingError::NotMapped);
         }
         let off = size.align_offset(vaddr.into());
-        Ok((entry.paddr() + off, entry.flags(), size))
+        Ok((entry.paddr().add(off), entry.flags(), size))
     }
 
     /// Maps a contiguous virtual memory region to a contiguous physical memory

diff --git a/page_table_multiarch/src/lib.rs b/page_table_multiarch/src/lib.rs
@@ -11,7 +11,7 @@ mod bits64;
 
 use core::{fmt::Debug, marker::PhantomData};
 
-use memory_addr::{PhysAddr, VirtAddr};
+use memory_addr::{MemoryAddr, PhysAddr, VirtAddr};
 
 pub use self::arch::*;
 pub use self::bits64::PageTable64;
@@ -55,7 +55,7 @@ pub trait PagingMetaData: Sync + Send {
     ///
     /// This associated type allows more flexible use of page tables structs like [`PageTable64`],
     /// for example, to implement EPTs.
-    type VirtAddr: Into<usize> + From<usize> + Copy;
+    type VirtAddr: MemoryAddr;
     // (^)it can be converted from/to usize and it's trivially copyable
 
     /// Whether a given physical address is valid.