feat(clang): add support for aarch64 clang

This commit fixes some issues when using clang:
- remove .directive .func which is not recognized by clang assembler;
- make gtlb_page_tables as no data to avoid section type mismatch;
- remove mov instructions with flexible second operand since ithey are
  not recognized by the clang assembler;

Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>
Signed-off-by: David Cerdeira <davidmcerdeira@gmail.com>

src/arch/armv8/aarch32/boot.S

@@ -184,7 +184,9 @@ _set_master_cpu:
 /*****  Helper functions for boot code. ******/
 
 .global boot_clear
+#ifdef CC_IS_GCC
 .func boot_clear
+#endif
 boot_clear:
 2:
     mov r8, #0
@@ -195,15 +197,19 @@ boot_clear:
 	b 2b
 1:
 	bx lr
+#ifdef CC_IS_GCC
 .endfunc
+#endif
 
 /*
  * Code adapted from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0"
  *
  * r0 - cache level to be invalidated (0 - dl1$, 1 - il1$)
  */
 .global boot_cache_invalidate
+#ifdef CC_IS_GCC
 .func boot_cache_invalidate
+#endif
 boot_cache_invalidate:
     mcr p15, 2, r0, c0, c0, 0 // write CSSELR (cache size selection)
     mrc p15, 1, r4, c0, c0, 0 // read CCSIDR (cache size id)
@@ -230,5 +236,7 @@ set_loop:
     cmp r5, r3 // last way reached yet?
     ble way_loop // if not, iterate way_loop
     bx lr
+#ifdef CC_IS_GCC
 .endfunc
+#endif
 

src/arch/armv8/aarch64/boot.S

@@ -62,7 +62,7 @@ _reset_handler:
 	 * this early in the initialization.
 	 */
 
-	mov x3, x0, lsr #8
+	lsr x3, x0, #8
 	and x3, x3, 0xff
 	adr x4, platform
 	ldr x4, [x4, PLAT_ARCH_OFF+PLAT_ARCH_CLUSTERS_OFF+PLAT_CLUSTERS_CORES_NUM_OFF]
@@ -180,7 +180,9 @@ _set_master_cpu:
 /***** 	Helper functions for boot code. ******/
 
 .global boot_clear
+#ifdef CC_IS_GCC
 .func boot_clear
+#endif
 boot_clear:
 2:
 	cmp	x16, x17
@@ -189,15 +191,19 @@ boot_clear:
 	b	2b
 1:
 	ret
+#ifdef CC_IS_GCC
 .endfunc
+#endif
 
 /*
  * Code taken from "Application Note Bare-metal Boot Code for ARMv8-A Processors - Version 1.0"
  *
  * x0 - cache level to be invalidated (0 - dl1$, 1 - il1$, 2 - l2$)
  */
 .global boot_cache_invalidate
+#ifdef CC_IS_GCC
 .func boot_cache_invalidate
+#endif
 boot_cache_invalidate:
 	msr csselr_el1, x0
 	mrs x4, ccsidr_el1 // read cache size id.
@@ -224,6 +230,8 @@ set_loop:
 	cmp x5, x3 // last way reached yet?
 	ble way_loop // if not, iterate way_loop
 	ret
+#ifdef CC_IS_GCC
 .endfunc
+#endif
 
 

src/arch/armv8/armv8-a/aarch64/boot.S

@@ -24,27 +24,27 @@ boot_arch_profile_init:
     ldr x18, =extra_allocated_phys_mem
 
 	/* Disable caches and MMU */
-	mrs x3, SCTLR_EL2 
-	bic x3, x3, #0x7	
-	msr SCTLR_EL2, x3 
-        
+	mrs x3, SCTLR_EL2
+	bic x3, x3, #0x7
+	msr SCTLR_EL2, x3
+
 	/* Skip initialy global page tables setup if not bsp (boot cpu) */
 	cbnz	x9, wait_for_bsp
 
-	adr	x16, _page_tables_start	
-	adr	x17, _page_tables_end	
+	adr	x16, _page_tables_start
+	adr	x17, _page_tables_end
 	add x16, x16, x18
 	add x17, x17, x18
-	bl	boot_clear		
+	bl	boot_clear
 
 	/* Set temporary flat mapping to switch to VAS. */
 
 	adr x4, root_l1_flat_pt
 	add x4, x4, x18
-	PTE_INDEX_ASM x5, x1, 1 
+	PTE_INDEX_ASM x5, x1, 1
 	add x6, x1, #(PTE_HYP_FLAGS | PTE_SUPERPAGE)
 	str x6, [x4, x5]
-	
+
 	/* Set global root mappings for hypervisor image */
 
 	adr x4, root_l1_pt
@@ -96,7 +96,7 @@ boot_arch_profile_init:
 	sev
 	b 	map_cpu
 
-wait_for_bsp:	
+wait_for_bsp:
 /* wait fot the bsp to finish up global mappings */
 	wfe
 	ldr x4, _boot_barrier
@@ -110,28 +110,28 @@ map_cpu:
 	 *    x5 -> pte index
 	 *    x6 -> phys addr
 	 *    x7 -> virt addr
-	 *    x8 -> aux 
+	 *    x8 -> aux
 	 */
 
 	/* get cpu root pt */
     adrp x3, _dmem_phys_beg
 	mov x8, #(CPU_SIZE + (PT_SIZE*PT_LVLS))
 	madd x3, x0, x8, x3
-	
-	mov	x16, x3	
+
+	mov	x16, x3
 	add	x17, x3, x8
 	bl	boot_clear
 
 	/* Get pointer to root page table */
 	add x4, x3, #CPU_SIZE
 
 	/* map original bootstrap flat mappings */
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	adr x6, root_l1_flat_pt
 	add x6, x6, x18
 	add x6, x6, #(PTE_HYP_FLAGS | PTE_TABLE)
 	str x6, [x4, x5]
-	
+
 	ldr x5, =(PTE_INDEX(0, BAO_VAS_BASE)*8)
 	adr x6, root_l1_pt
 	add x6, x6, x18
@@ -174,7 +174,7 @@ setup_cpu:
 	/**
 	 * The operation is purposely commented out.  We are assuming monitor code already enabled smp
 	 * coherency.
-	 */ 
+	 */
 
 	/* setup translation configurations */
 	ldr x3, =TCR_EL2_DFLT
@@ -194,7 +194,7 @@ setup_cpu:
 	add x3, x3, #CPU_SIZE
 	msr TTBR0_EL2, x3
 
-	/**	
+	/**
 	 * TODO: set implementation defined registers such as ACTLR or AMAIR. Maybe define a macro for
 	 * this in a implementation oriented directory inside arch.
 	 */
@@ -208,11 +208,11 @@ setup_cpu:
 	/* Enable MMU and caches */
 	ldr x4, =(SCTLR_RES1 | SCTLR_M | SCTLR_C | SCTLR_I)
 	msr	SCTLR_EL2, x4
-	
+
 	tlbi	alle2
 	dsb	nsh
 	isb
-	
+
 	br  x5
 
 _enter_vas:
@@ -224,7 +224,7 @@ _enter_vas:
 	/* Remove temporary mapping - the L1 page holding it leaks */
 	ldr x4, =BAO_CPU_BASE
 	add x4, x4, #CPU_SIZE
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	str xzr, [x4, x5]
 
     tlbi	alle2
@@ -237,7 +237,9 @@ _enter_vas:
     ret
 
 .global psci_boot_entry
+#ifdef CC_IS_GCC
 .func psci_boot_entry
+#endif
 psci_boot_entry:
 warm_boot:
 
@@ -272,7 +274,7 @@ warm_boot:
 	/* map original bootstrap flat mappings */
 	mrs x3, TTBR0_EL2
 	adrp x1, _image_start
-	PTE_INDEX_ASM x1, x1, 0 
+	PTE_INDEX_ASM x1, x1, 0
 	add x3, x3, x1
 	dc civac, x3  //we invalidated l1$, but make sure the pte is not in l2$
 	add x5, x5, #(PTE_HYP_FLAGS | PTE_TABLE)
@@ -282,7 +284,7 @@ warm_boot:
 	ldr	x3, =_hyp_vector_table
 	msr	VBAR_EL2, x3
 
-    tlbi	alle2 
+    tlbi	alle2
 	dsb	nsh
 	isb
 
@@ -292,17 +294,17 @@ warm_boot:
 
 	dsb	nsh
 	isb
-	
+
 	ldr x5, =_enter_vas_warm
-	br  x5		
+	br  x5
 
 _enter_vas_warm:
 	/* Unmap bootstrat flat mappings */
 	ldr x4, =BAO_CPU_BASE
 	add x3, x4, #(CPU_STACK_OFF+CPU_STACK_SIZE)
 
 	add x4, x4, #CPU_SIZE
-	PTE_INDEX_ASM x5, x1, 0 
+	PTE_INDEX_ASM x5, x1, 0
 	str xzr, [x4, x5]
     tlbi	alle2
 	dsb	nsh
@@ -314,4 +316,6 @@ _enter_vas_warm:
 	bl	psci_wake
 	b 	.
 
+#ifdef CC_IS_GCC
 .endfunc
+#endif

src/arch/armv8/armv8-a/pagetables.S

@@ -5,7 +5,7 @@
 
 #include <arch/page_table.h>
 
-.section .glb_page_tables, "aw"
+.section .glb_page_tables, "aw", @nobits
 
 .globl root_l1_pt
 .balign PAGE_SIZE, 0