ibex_wb

RISC-V Ibex core with Wishbone B4 interface.

Design

The instruction and data memory interfaces are converted to Wishbone. These examples use shared bus interconnection between masters (instruction bus, data bus) and slaves (e.g. memory, LED driver). For better throughput or latency a crossbar interconnect can be considered.

Ibex memory control vs. Wishbone bus

Basic Memory Transaction

Back-to-back Memory Transaction

Slow Response Memory Transaction

Status

Simulated with Synopsys VCS.

Timing with uncompressed instructions

Program	Cycles	Instructions	CPI
crc_32	43277	24714	1.75
fib	172	107	1.61
led	509993	382481	1.33
nettle-aes	118693	63235	1.88
		mean	1.64

Timing with compressed instructions

Program	Cycles	Instructions	CPI
crc_32	37105	23687	1.57
fib	165	107	1.54
led	509993	382492	1.33
nettle-aes	113482	63235	1.79
		mean	1.56

FPGA Implementation

Intel/Cyclone-V

Cyclone V GX Starter Kit

For Quartus 19.1 use branch fpga_quartus in submodules common_cells, ibex andriscv-dbg.

Xilinx/Artix-7

Arty A7-100T

For Vivado 2019.2 use branch master in all submodules.

Recources

• Wishbone at opencores.org
• ZipCPU for a deeper understanding of the pipelined mode.