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preempt improvements (esp-rs#185)
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* [Xtensa] ensure CPU interrupts are re-enabled

Once the scheduler is enabled.

* [Xtensa] preempt: reduce from 2000hz -> 1000hz

This brings the task switching hz inline with the values for the RISCV
chips

* reduce preempt hz to 100 (freertos default)

* remove WIFI_BB interrupt from esp32_timer

* fix typo in timer_esp32s3
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@MabezDev @bjoernQ
MabezDev authored and bjoernQ committed May 23, 2024
1 parent f8ee235 commit 3925e40
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Showing 6 changed files with 27 additions and 50 deletions.
37 changes: 7 additions & 30 deletions esp-wifi/src/timer_esp32.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ pub const TICKS_PER_SECOND: u64 = 40_000_000;
pub const COUNTER_BIT_MASK: u64 = 0xFFFF_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(4000);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(500);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(100);

static TIMER1: Mutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> = Mutex::new(RefCell::new(None));

Expand Down Expand Up @@ -54,13 +54,6 @@ pub fn setup_timer_isr(timg1_timer0: Timer<Timer0<TIMG1>>) {
)
.unwrap();

#[cfg(feature = "wifi")]
interrupt::enable(
peripherals::Interrupt::WIFI_BB,
interrupt::Priority::Priority1,
)
.unwrap();

#[cfg(feature = "ble")]
{
interrupt::enable(peripherals::Interrupt::RWBT, interrupt::Priority::Priority1).unwrap();
Expand All @@ -77,20 +70,20 @@ pub fn setup_timer_isr(timg1_timer0: Timer<Timer0<TIMG1>>) {
}

timer1.listen();
timer1.start(TIMER_DELAY.convert());
timer1.start(TIMER_DELAY.into_duration());
critical_section::with(|cs| {
TIMER1.borrow_ref_mut(cs).replace(timer1);
});

xtensa_lx::timer::set_ccompare0(0xffffffff);

unsafe {
xtensa_lx::interrupt::disable();
let enabled = esp32_hal::xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
1 << 6 // Timer0
| 1 << 29 // Software1
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask(),
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() | enabled,
);
}

Expand Down Expand Up @@ -134,22 +127,6 @@ fn WIFI_MAC() {
}
}

#[cfg(feature = "wifi")]
#[interrupt]
fn WIFI_BB() {
unsafe {
let (fnc, arg) = crate::wifi::os_adapter::ISR_INTERRUPT_1;
trace!("interrupt WIFI_BB {:p} {:p}", fnc, arg);

if !fnc.is_null() {
let fnc: fn(*mut crate::binary::c_types::c_void) = core::mem::transmute(fnc);
fnc(arg);
}

trace!("interrupt 1 done");
};
}

#[cfg(feature = "ble")]
#[interrupt]
fn RWBT() {
Expand Down Expand Up @@ -202,7 +179,7 @@ fn TG1_T0_LEVEL(context: &mut Context) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand All @@ -222,7 +199,7 @@ fn Software1(_level: u32, context: &mut Context) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand Down
4 changes: 2 additions & 2 deletions esp-wifi/src/timer_esp32c2.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ pub const TICKS_PER_SECOND: u64 = 16_000_000;
pub const COUNTER_BIT_MASK: u64 = 0x000F_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(500);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(1_000);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(100);

static ALARM0: Mutex<RefCell<Option<Alarm<Periodic, 0>>>> = Mutex::new(RefCell::new(None));

Expand Down
4 changes: 2 additions & 2 deletions esp-wifi/src/timer_esp32c3.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ pub const TICKS_PER_SECOND: u64 = 16_000_000;
pub const COUNTER_BIT_MASK: u64 = 0x000F_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(500);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(1_000);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(100);

static ALARM0: Mutex<RefCell<Option<Alarm<Periodic, 0>>>> = Mutex::new(RefCell::new(None));

Expand Down
4 changes: 2 additions & 2 deletions esp-wifi/src/timer_esp32c6.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ pub const TICKS_PER_SECOND: u64 = 16_000_000;
pub const COUNTER_BIT_MASK: u64 = 0x000F_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(500);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(1_000);
const TIMER_DELAY: fugit::HertzU32 = fugit::HertzU32::from_raw(100);

static ALARM0: Mutex<RefCell<Option<Alarm<Periodic, 0>>>> = Mutex::new(RefCell::new(None));

Expand Down
14 changes: 7 additions & 7 deletions esp-wifi/src/timer_esp32s2.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ pub const TICKS_PER_SECOND: u64 = 40_000_000;
pub const COUNTER_BIT_MASK: u64 = 0xFFFF_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(4000);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(500);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(100);

static TIMER1: Mutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> = Mutex::new(RefCell::new(None));

Expand Down Expand Up @@ -62,20 +62,20 @@ pub fn setup_timer_isr(timg1_timer0: Timer<Timer0<TIMG1>>) {
.unwrap();

timer1.listen();
timer1.start(TIMER_DELAY.convert());
timer1.start(TIMER_DELAY.into_duration());
critical_section::with(|cs| {
TIMER1.borrow_ref_mut(cs).replace(timer1);
});

xtensa_lx::timer::set_ccompare0(0xffffffff);

unsafe {
xtensa_lx::interrupt::disable();
let enabled = esp32s2_hal::xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
1 << 6 // Timer0
| 1 << 29 // Software1
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask(),
| xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() | enabled,
);
}

Expand Down Expand Up @@ -131,7 +131,7 @@ fn TG1_T0_LEVEL(context: &mut Context) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand All @@ -151,7 +151,7 @@ fn Software1(_level: u32, context: &mut Context) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand Down
14 changes: 7 additions & 7 deletions esp-wifi/src/timer_esp32s3.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ pub const TICKS_PER_SECOND: u64 = 40_000_000;
pub const COUNTER_BIT_MASK: u64 = 0xFFFF_FFFF_FFFF_FFFF;

#[cfg(debug_assertions)]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(4000);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(50);
#[cfg(not(debug_assertions))]
const TIMER_DELAY: fugit::MicrosDurationU64 = fugit::MicrosDurationU64::micros(500);
const TIMER_DELAY: fugit::HertzU64 = fugit::HertzU64::from_raw(100);

static TIMER1: Mutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> = Mutex::new(RefCell::new(None));

Expand Down Expand Up @@ -74,20 +74,20 @@ pub fn setup_timer_isr(timg1_timer0: Timer<Timer0<TIMG1>>) {
}

timer1.listen();
timer1.start(TIMER_DELAY.convert());
timer1.start(TIMER_DELAY.into_duration());
critical_section::with(|cs| {
TIMER1.borrow_ref_mut(cs).replace(timer1);
});

esp32s3_hal::xtensa_lx::timer::set_ccompare0(0xffffffff);

unsafe {
esp32s3_hal::xtensa_lx::interrupt::disable();
let enabled = esp32s3_hal::xtensa_lx::interrupt::disable();
esp32s3_hal::xtensa_lx::interrupt::enable_mask(
1 << 6 // Timer0
| 1 << 29 // Software1
| esp32s3_hal::xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()
| esp32s3_hal::xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask(),
| esp32s3_hal::xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() | enabled,
);
}

Expand Down Expand Up @@ -169,7 +169,7 @@ fn TG1_T0_LEVEL(context: &mut TrapFrame) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand All @@ -189,7 +189,7 @@ fn Software1(_level: u32, context: &mut TrapFrame) {
let mut timer = TIMER1.borrow_ref_mut(cs);
let timer = timer.as_mut().unwrap();
timer.clear_interrupt();
timer.start(TIMER_DELAY.convert());
timer.start(TIMER_DELAY.into_duration());
});
}

Expand Down

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