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Rollup merge of rust-lang#112168 - scottmcm:lower-div-rem-unchecked-t…
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…o-mir, r=oli-obk

Lower `unchecked_div`/`_rem` to MIR's `BinOp::Div`/`Rem`

As described in <https://doc.rust-lang.org/nightly/nightly-rustc/rustc_middle/mir/enum.BinOp.html#variant.Div>, the ordinary `BinOp`s for these are already UB for division by zero ([or overflow](https://llvm.org/docs/LangRef.html#sdiv-instruction), [demo](https://rust.godbolt.org/z/71e7P7Exh)), as MIR building is responsible for inserting code to panic for those cases regardless of whether the overflow checks are enabled.

So we can lower these in the same arm that lowers `wrapping_add` to MIR `BinOp::Add` and such, as all these cases turn into ordinary `Rvalue::BinaryOp`s.
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compiler-errors authored Jun 2, 2023
2 parents fcd93ac + 919da2f commit 4ecd45a
Showing 1 changed file with 1 addition and 4 deletions.
5 changes: 1 addition & 4 deletions src/intrinsics/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -475,9 +475,7 @@ fn codegen_regular_intrinsic_call<'tcx>(
sym::unchecked_add
| sym::unchecked_sub
| sym::unchecked_mul
| sym::unchecked_div
| sym::exact_div
| sym::unchecked_rem
| sym::unchecked_shl
| sym::unchecked_shr => {
intrinsic_args!(fx, args => (x, y); intrinsic);
Expand All @@ -487,8 +485,7 @@ fn codegen_regular_intrinsic_call<'tcx>(
sym::unchecked_add => BinOp::Add,
sym::unchecked_sub => BinOp::Sub,
sym::unchecked_mul => BinOp::Mul,
sym::unchecked_div | sym::exact_div => BinOp::Div,
sym::unchecked_rem => BinOp::Rem,
sym::exact_div => BinOp::Div,
sym::unchecked_shl => BinOp::Shl,
sym::unchecked_shr => BinOp::Shr,
_ => unreachable!(),
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