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Rename v8x16.shuffle1 and v8x16.shuffle2_imm to v8x16.swizzle and v8x…
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…16.shuffle_imm.
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nlewycky committed Jul 18, 2019
1 parent b7c4a68 commit dfc6f3d
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Showing 3 changed files with 6 additions and 6 deletions.
4 changes: 2 additions & 2 deletions src/binary_reader.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1418,13 +1418,13 @@ impl<'a> BinaryReader<'a> {
0xb0 => Operator::F32x4ConvertUI32x4,
0xb1 => Operator::F64x2ConvertSI64x2,
0xb2 => Operator::F64x2ConvertUI64x2,
0xc0 => Operator::V8x16Shuffle1,
0xc0 => Operator::V8x16Swizzle,
0xc1 => {
let mut lanes = [0 as SIMDLaneIndex; 16];
for i in 0..16 {
lanes[i] = self.read_lane_index(32)?
}
Operator::V8x16Shuffle2Imm { lanes }
Operator::V8x16ShuffleImm { lanes }
}
_ => {
return Err(BinaryReaderError {
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4 changes: 2 additions & 2 deletions src/operators_validator.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1486,12 +1486,12 @@ impl OperatorValidator {
self.check_operands_2(Type::V128, Type::I32)?;
self.func_state.change_frame_with_type(2, Type::V128)?;
}
Operator::V8x16Shuffle1 => {
Operator::V8x16Swizzle => {
self.check_simd_enabled()?;
self.check_operands_2(Type::V128, Type::V128)?;
self.func_state.change_frame_with_type(2, Type::V128)?;
}
Operator::V8x16Shuffle2Imm { ref lanes } => {
Operator::V8x16ShuffleImm { ref lanes } => {
self.check_simd_enabled()?;
self.check_operands_2(Type::V128, Type::V128)?;
for i in lanes {
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4 changes: 2 additions & 2 deletions src/primitives.rs
Original file line number Diff line number Diff line change
Expand Up @@ -650,6 +650,6 @@ pub enum Operator<'a> {
F32x4ConvertUI32x4,
F64x2ConvertSI64x2,
F64x2ConvertUI64x2,
V8x16Shuffle1,
V8x16Shuffle2Imm { lanes: [SIMDLaneIndex; 16] },
V8x16Swizzle,
V8x16ShuffleImm { lanes: [SIMDLaneIndex; 16] },
}

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