change while line to for line due to format checking

calyxir · Dec 17, 2024 · cdcfb9c · cdcfb9c
1 parent 3300c40
commit cdcfb9c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
@@ -235,10 +235,10 @@ impl Backend for VerilogBackend {
             if cmd.status.success() {
                 // Post-process morty output
                 let stdout = String::from_utf8_lossy(&cmd.stdout);
-                let mut lines = stdout.lines();
+                let lines = stdout.lines();
                 let mut skip_next_line = false;
 
-                while let Some(line) = lines.next() {
+                for line in lines {
                     if skip_next_line {
                         skip_next_line = false;
                         continue;