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Cherry-pick from next for v5.0.1 #2141

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merged 9 commits into from
Aug 21, 2023
Merged

Cherry-pick from next for v5.0.1 #2141

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0008401
Add Python bindings for WASM
peace-maker Jul 13, 2023
9984898
Update Python bindings for m68k
peace-maker Jul 13, 2023
29175cf
Update Python bindings for mos65xx
peace-maker Jul 13, 2023
d3d0ab0
Update Python bindings for x86
peace-maker Jul 13, 2023
5b05bcb
Add Python bindings for SH
peace-maker Jul 13, 2023
b8febfe
Update CS_* constants in Python bindings
peace-maker Jul 13, 2023
d2a39a2
Update constants from ARM auto-sync patch
peace-maker Jul 19, 2023
a3ad50e
Fixing TriCore disasm instructions (#2088)
bkoppelmann Jul 26, 2023
c703d96
allow absolute CMAKE_INSTALL_*DIR (#2134)
chayleaf Aug 9, 2023
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1 change: 1 addition & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,7 @@ tests/test_evm
tests/test_wasm
tests/test_mos65xx
tests/test_bpf
tests/test_sh
tests/test_riscv

# regress binaries
Expand Down
121 changes: 99 additions & 22 deletions arch/TriCore/TriCoreDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -425,6 +425,7 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6);
unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4);
unsigned off10 = (off10_0 << 0) | (off10_1 << 6);
bool is_store = false;

unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
Expand All @@ -440,32 +441,83 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder);
}

if (desc->NumOperands == 2) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
switch (MCInst_getOpcode(Inst)) {
case TRICORE_ST_A_bo_r:
case TRICORE_ST_A_bo_c:
case TRICORE_ST_B_bo_r:
case TRICORE_ST_B_bo_c:
case TRICORE_ST_D_bo_r:
case TRICORE_ST_D_bo_c:
case TRICORE_ST_DA_bo_r:
case TRICORE_ST_DA_bo_c:
case TRICORE_ST_H_bo_r:
case TRICORE_ST_H_bo_c:
case TRICORE_ST_Q_bo_r:
case TRICORE_ST_Q_bo_c:
case TRICORE_ST_W_bo_r:
case TRICORE_ST_W_bo_c:
case TRICORE_SWAP_W_bo_r:
case TRICORE_SWAP_W_bo_c:
case TRICORE_SWAPMSK_W_bo_c:
case TRICORE_SWAPMSK_W_bo_r: {
is_store = true;
break;
}
}

if (desc->NumOperands == 2) {
if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) {
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
// we have [reg+r] instruction
if (is_store) {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
} else {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
}
} else {
// we have one of the CACHE instructions without destination reg
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

MCOperand_CreateImm0(Inst, off10);
}
return MCDisassembler_Success;
}

if (desc->NumOperands > 2) {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (is_store) {
// we have [reg+c] instruction
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
} else {
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0],
Decoder);
if (status != MCDisassembler_Success)
return status;

status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
}
MCOperand_CreateImm0(Inst, off10);
}

Expand Down Expand Up @@ -649,8 +701,13 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
MCOperand_CreateImm0(Inst, const16);
} else {
MCOperand_CreateImm0(Inst, const16);
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
if (MCInst_getOpcode(Inst) == TRICORE_MTCR_rlc) {
status =
DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder);
} else {
status =
DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder);
}
if (status != MCDisassembler_Success)
return status;
}
Expand Down Expand Up @@ -699,10 +756,24 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
}

if (desc->NumOperands > 1) {
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
if (status != MCDisassembler_Success)
return status;
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
switch (MCInst_getOpcode(Inst)) {
case TRICORE_ABSS_rr:
case TRICORE_ABSS_H_rr:
case TRICORE_ABS_H_rr:
case TRICORE_ABS_B_rr:
case TRICORE_ABS_rr: {
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1],
Decoder);
break;
default:
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1],
Decoder);
}
if (status != MCDisassembler_Success)
return status;
}
}
}

if (desc->NumOperands > 2) {
Expand Down Expand Up @@ -1259,7 +1330,13 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
return status;

if (desc->NumOperands == 3) {
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
switch (MCInst_getOpcode(Inst)) {
case TRICORE_EXTR_rrrr:
case TRICORE_EXTR_U_rrrr:
return DecodeRegisterClass(Inst, s3, &desc->OpInfo[2], Decoder);
default:
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder);
}
}

// Decode s2.
Expand Down
16 changes: 16 additions & 0 deletions arch/TriCore/TriCoreInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -224,6 +224,19 @@ static void off4_fixup(MCInst *MI, uint64_t *off4)
}
}

static void const8_fixup(MCInst *MI, uint64_t *const8)
{
switch (MCInst_getOpcode(MI)) {
case TRICORE_LD_A_sc:
case TRICORE_ST_A_sc:
case TRICORE_ST_W_sc:
case TRICORE_LD_W_sc: {
*const8 *= 4;
break;
}
}
}

static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
Expand All @@ -235,6 +248,9 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n)
if (n == 4) {
off4_fixup(MI, &imm);
}
if (n == 8) {
const8_fixup(MI, &imm);
}

printInt64Bang(O, imm);
fill_imm(MI, imm);
Expand Down
3 changes: 2 additions & 1 deletion bindings/const_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

INCL_DIR = '../include/capstone/'

include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'tricore.h' ]
include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h' ]

template = {
'java': {
Expand Down Expand Up @@ -53,6 +53,7 @@
'mos65xx.h': 'mos65xx',
'bpf.h': 'bpf',
'riscv.h': 'riscv',
'sh.h': 'sh',
'tricore.h': ['TRICORE', 'TriCore'],
'comment_open': '#',
'comment_close': '',
Expand Down
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