Fix write cache to be LRU

3d184aa unintentionally made the write
cache evict randomly. This fixes it to be LRU just like the read cache.

This speeds up some workloads, like ord indexing, by a factor of 4x or
more

src/tree_store/page_store/cached_file.rs

@@ -88,17 +88,19 @@ impl LRUWriteCache {
     }
 
     fn pop_lowest_priority(&mut self) -> Option<(u64, Arc<[u8]>)> {
-        let mut selected = None;
-        for (k, v) in self.cache.iter() {
-            if v.is_some() {
-                selected = Some(*k);
+        for _ in 0..self.cache.len() {
+            if let Some((k, v)) = self.cache.pop_lowest_priority() {
+                if let Some(v_inner) = v {
+                    return Some((k, v_inner));
+                } else {
+                    // Value is borrowed by take_value(). We can't evict it, so put it back.
+                    self.cache.insert(k, v);
+                }
+            } else {
+                break;
             }
         }
-        if let Some(key) = selected {
-            self.cache.remove(&key).map(|x| (key, x.unwrap()))
-        } else {
-            None
-        }
+        None
     }
 
     fn clear(&mut self) {

src/tree_store/page_store/lru_cache.rs

@@ -16,6 +16,10 @@ impl<T> LRUCache<T> {
         }
     }
 
+    pub(crate) fn len(&self) -> usize {
+        self.cache.len()
+    }
+
     pub(crate) fn insert(&mut self, key: u64, value: T) -> Option<T> {
         let result = self
             .cache