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Serial Wire Debug Open Library is distributed under 3-clause BSD license. | ||
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Copyright (C) 2010-2011, Tomasz Boleslaw CEDRO (http://www.tomek.cedro.info) | ||
All rights reserved. | ||
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Redistribution and use in source and binary forms, with or without | ||
modification, are permitted provided that the following conditions are met: | ||
1. Redistributions of source code must retain the above copyright notice, | ||
this list of conditions and the following disclaimer. | ||
2. Redistributions in binary form must reproduce the above copyright notice, | ||
this list of conditions and the following disclaimer in the documentation | ||
and/or other materials provided with the distribution. | ||
3. Neither the name of the Tomasz Boleslaw CEDRO nor the names of its | ||
contributors may be used to endorse or promote products derived from this | ||
software without specific prior written permission. | ||
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS | ||
BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, | ||
OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | ||
IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | ||
OF THE POSSIBILITY OF SUCH DAMAGE.* | ||
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Written by Tomasz Boleslaw CEDRO <tomek@cedro.info>, 2010-2011; |
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LibSWD-0.1 (2011-04-02): | ||
Initial release of LibSWD: | ||
* Basic functionality of transport, queue and drivers for ADIv5.0. | ||
* Automated SW-DP activation/reset and IDCODE read. | ||
* Tested and verified functionality on UrJTAG. | ||
* Source code documented using Doxygen. | ||
* Autotools integration for standarized build. | ||
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include $(top_srcdir)/aminclude.am | ||
SUBDIRS = src | ||
ACLOCAL_AMFLAGS = -I m4 | ||
nobase_dist_pkgdata_DATA = doc/libswd-0.1.pdf |
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2011-04-02: | ||
----------- | ||
* LibSWD initial version 0.1 released to the public. | ||
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2011-03-23: | ||
----------- | ||
* Integration with UrJTAG complete. Source code sent to developers. | ||
* Functionality verification complete. Updated work in progress description | ||
at http://stm32primer2swd.sourceforge.net/ | ||
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2011-02-09: | ||
----------- | ||
* Remote source code repository (SVN) started. | ||
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2010-12-29: | ||
----------- | ||
* Official LibSWD project website launched at http://libswd.sf.net | ||
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2010-11-23: | ||
----------- | ||
* Decision to implement SWD API as standalone library. | ||
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2010-10-21: | ||
----------- | ||
* Work to create open swd implementation has begun. | ||
* Website with progress log launched at http://stm32primer2swd.sourceforge.net/. |
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Serial Wire Debug Open Library Readme File | ||
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1. General information. | ||
2. How to build and install. | ||
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---------------------- | ||
1. General information | ||
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Serial Wire Debug Open Library is first open solution for accessing the SW-DP (Serial Wire Debug Port) on ARM Cortex CPU based embedded systems. Library is available under "new" 3 clause BSD License. This project was started by Tomek Cedro to create and document Free and Open-Source SWD (Serial Wire Debug) access to new ARM-Cortex CPU cores. SWD is an alternative to JTAG method for accessing the DAP that allows low-level access to system resources such as system bus, memory, IO, even single stepping the code execution - a must-have for an embedded systems developer. | ||
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SWD works on both simple and advanced devices from the ARM Cortex family. By default Cortex CPU or FPGA'a IP Core is both JTAG and SWD capable, so the common name for this transport method is SWJ (Serial Wire and JTAG). It is the application requirement and designer choice if a final product supports JTAG, SWD, or both (SWJ). | ||
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LibSWD can be considered almost standalone to be easily integrated into third party software with minimal impact on existing program structure. LibSWD implements all utilities necessary to generate bit stream and queue bus operations on both high (operation) and low (bit) abstraction level. High level functions can be called from external application to generate queue that represent bus operations or simply produce a bitstream that can be later flushed into real hardware with simple set of functions (these functions can utilise existing cable drivers already implemented in external software). | ||
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The first approach and practical tests were performed on simple STM32Primer development kits using UrJTAG and OpenOCD utilities as described on the http://stm32primer2.sf.net project webstie. Major parts of this research were conducted as a cooperation between Orange Labs Warsaw and Orange Labs Paris, and some additionally by Cybernetic Research Student Group from Warsaw University of Technology in Poland that I am founder and member. | ||
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For more information please visit project website at http://libswd.sf.net. | ||
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---------------------------- | ||
2. How to build and install. | ||
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To obtain the latest release visit project website at http://libswd.sf.net. LibSWD use Autotools so the build and install procedure is pretty straightforward: | ||
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tar xjvf libswd-<version>.tar.bz2 | ||
cd libswd-<version> | ||
./configure <optional parameters> | ||
make install clean | ||
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It is possible to build the documentation in html, pdf or both formats. Note that you need to have Doxygen installed for this to work. Additionally you need to have LaTeX installed to build the PDF. | ||
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make doxygen-pdf | ||
make doxygen-html | ||
make doxygen-doc | ||
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To create package file for distribution type: | ||
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make distcheck | ||
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To uninstall the library type: | ||
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make uninstall | ||
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