Merge pull request #1 from silee2/fix_inclusion

Fix macro names of headers to follow MLIR standard.
chencha3 · Jan 11, 2024 · 4b9d7de · 4b9d7de
2 parents 90bb390 + 39f73f2
commit 4b9d7de
Show file tree

Hide file tree

Showing 6 changed files with 18 additions and 18 deletions.
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_OPS_H_INCLUDED_
-#define _XeGPU_OPS_H_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPU_H
+#define MLIR_DIALECT_XEGPU_IR_XEGPU_H
 
 #include <mlir/IR/BuiltinTypes.h>
 #include <mlir/IR/Dialect.h>
@@ -49,4 +49,4 @@ class TensorDescType;
 #define GET_OP_CLASSES
 #include <mlir/Dialect/XeGPU/IR/XeGPU.h.inc>
 
-#endif // _XeGPU_OPS_H_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPU_H
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.td
@@ -6,9 +6,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_TD_INCLUDED_
-#define _XeGPU_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPU_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPU_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUOps.td"
 
-#endif // _XeGPU_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPU_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_ATTRS_TD_INCLUDED_
-#define _XEGPU_ATTRS_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
 
@@ -133,4 +133,4 @@ def XeGPU_AtomicRMWKindAttr : I64EnumAttr<
   let cppNamespace = "::mlir::xegpu";
 }
 
-#endif // _XEGPU_ATTRS_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_DIALECT_TD_INCLUDED_
-#define _XEGPU_DIALECT_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
 
 include "mlir/IR/OpBase.td"
 include "mlir/IR/OpAsmInterface.td"
@@ -51,4 +51,4 @@ def XeGPUDialect : Dialect {
     let useDefaultAttributePrinterParser = true;
 }
 
-#endif //XEGPU_DIALECT
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XeGPU_OPS_TD_INCLUDED_
-#define _XeGPU_OPS_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 
 include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td"
 include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
@@ -584,4 +584,4 @@ def XeGPU_MfenceOp
       }];
   }
 
-#endif // _XeGPU_OPS_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef _XEGPU_TYPES_TD_INCLUDED_
-#define _XEGPU_TYPES_TD_INCLUDED_
+#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD
+#define MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD
 
 include "mlir/IR/BuiltinTypes.td"
 
@@ -168,4 +168,4 @@ def XeGPU_Nbarrier: XeGPUTypeDef<"Nbarrier", "nbarrier", [], "mlir::Type"> {
   }];
 }
 
-#endif // _XEGPU_TYPES_TD_INCLUDED_
+#endif // MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD