Prepare for release

chipsalliance · Sep 13, 2021 · ac793e1 · ac793e1
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diff --git a/README.md b/README.md
@@ -275,7 +275,7 @@ Another example to run is the Zephyr philosophers demo.
         ├──fusesoc_libraries
         └──riscv-compliance
 
-3. Enter the riscv-compliance directory and run `make TARGETDIR=$SWERVOLF_ROOT/riscv-target RISCV_TARGET=swerv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$WORKSPACE/build/swervolf_0.7.3/sim-verilator/Vswervolf_core_tb`
+3. Enter the riscv-compliance directory and run `make TARGETDIR=$SWERVOLF_ROOT/riscv-target RISCV_TARGET=swerv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$WORKSPACE/build/swervolf_0.7.4/sim-verilator/Vswervolf_core_tb`
 
 *Note: Other test suites can be run by replacing RISCV_ISA=rv32imc with rv32im or rv32i*
 

diff --git a/swervolf.core b/swervolf.core
@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : ::swervolf:0.7.3
+name : ::swervolf:0.7.4
 description : Reference SoC for the SweRV family of cores
 
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