Update RTL

The adams-bridge is now a submodule of the rtl.

Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>

.gitmodules

@@ -12,6 +12,3 @@
 [submodule "hw/latest/i3c-core-rtl"]
 	path = hw/latest/i3c-core-rtl
 	url = https://github.com/chipsalliance/i3c-core.git
-[submodule "hw/latest/adams-bridge"]
-	path = hw/latest/adams-bridge
-	url = https://github.com/chipsalliance/adams-bridge.git

hw/latest/registers/src/axi_dma.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -1719,10 +1719,25 @@ pub mod regs {
         pub fn axi_dma_fsm_ps(&self) -> super::enums::AxiDmaFsmE {
             super::enums::AxiDmaFsmE::try_from((self.0 >> 16) & 3).unwrap()
         }
+        /// Payload Available. Signal indicates data is available.
+        /// When the DMA is active and was armed with nonzero block
+        /// size, this is used by the hardware to automatically
+        /// trigger AXI transactions of the specified block
+        /// size, until the total byte count is transferred.
+        #[inline(always)]
+        pub fn payload_available(&self) -> bool {
+            ((self.0 >> 18) & 1) != 0
+        }
+        /// Image Activated. Signal indicates image activation status
+        /// reported by Recovery Interface (from Caliptra Subsystem).
+        #[inline(always)]
+        pub fn image_activated(&self) -> bool {
+            ((self.0 >> 19) & 1) != 0
+        }
         /// RESERVED.
         #[inline(always)]
         pub fn rsvd1(&self) -> u32 {
-            (self.0 >> 18) & 0x3fff
+            (self.0 >> 20) & 0xfff
         }
     }
     impl From<u32> for Status0ReadVal {

hw/latest/registers/src/csrng.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/doe.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/dv.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/ecc.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/el2_pic_ctrl.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/entropy_src.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/hmac.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -697,10 +697,15 @@ pub mod regs {
         pub fn mode(self, val: bool) -> Self {
             Self((self.0 & !(1 << 3)) | (u32::from(val) << 3))
         }
+        /// CSR Mode: Indicates to the HMAC512 core to use the CSR HMAC key
+        #[inline(always)]
+        pub fn csr_mode(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+        }
         /// Reserved
         #[inline(always)]
         pub fn reserved(self, val: bool) -> Self {
-            Self((self.0 & !(1 << 4)) | (u32::from(val) << 4))
+            Self((self.0 & !(1 << 5)) | (u32::from(val) << 5))
         }
     }
     impl From<u32> for Hmac512CtrlWriteVal {

hw/latest/registers/src/i3ccsr.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/kv.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -77,7 +77,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     ///
     /// Read value: [`kv::regs::KvctrlReadVal`]; Write value: [`kv::regs::KvctrlWriteVal`]
     #[inline(always)]
-    pub fn key_ctrl(&self) -> ureg::Array<32, ureg::RegRef<crate::kv::meta::KeyCtrl, &TMmio>> {
+    pub fn key_ctrl(&self) -> ureg::Array<24, ureg::RegRef<crate::kv::meta::KeyCtrl, &TMmio>> {
         unsafe {
             ureg::Array::new_with_mmio(
                 self.ptr.wrapping_add(0 / core::mem::size_of::<u32>()),
@@ -91,7 +91,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     #[inline(always)]
     pub fn key_entry(
         &self,
-    ) -> ureg::Array<32, ureg::Array<12, ureg::RegRef<crate::kv::meta::KeyEntry, &TMmio>>> {
+    ) -> ureg::Array<24, ureg::Array<16, ureg::RegRef<crate::kv::meta::KeyEntry, &TMmio>>> {
         unsafe {
             ureg::Array::new_with_mmio(
                 self.ptr.wrapping_add(0x600 / core::mem::size_of::<u32>()),
@@ -200,7 +200,7 @@ pub mod regs {
         /// Destination valid bits stored as an array for ease of use in RTL.
         /// [br]dest_valid[0] = hmac_key_dest_valid
         /// [br]dest_valid[1] = hmac_block_dest_valid
-        /// [br]dest_valid[2] = sha_block_dest_valid
+        /// [br]dest_valid[2] = mldsa_seed_dest_valid
         /// [br]dest_valid[3] = ecc_pkey_dest_valid
         /// [br]dest_valid[4] = ecc_seed_dest_valid
         /// [br]dest_valid[5] = rsvd

hw/latest/registers/src/lib.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![no_std]
 #![allow(clippy::erasing_op)]
@@ -141,9 +141,9 @@ pub mod regs {
         pub fn hmac_block_dest_valid(&self) -> bool {
             ((self.0 >> 7) & 1) != 0
         }
-        /// Reserved field. No SHA key vault interface
+        /// MLDSA_SEED is a valid destination
         #[inline(always)]
-        pub fn sha_block_dest_valid(&self) -> bool {
+        pub fn mldsa_seed_dest_valid(&self) -> bool {
             ((self.0 >> 8) & 1) != 0
         }
         /// ECC PKEY is a valid destination
@@ -203,9 +203,9 @@ pub mod regs {
         pub fn hmac_block_dest_valid(self, val: bool) -> Self {
             Self((self.0 & !(1 << 7)) | (u32::from(val) << 7))
         }
-        /// Reserved field. No SHA key vault interface
+        /// MLDSA_SEED is a valid destination
         #[inline(always)]
-        pub fn sha_block_dest_valid(self, val: bool) -> Self {
+        pub fn mldsa_seed_dest_valid(self, val: bool) -> Self {
             Self((self.0 & !(1 << 8)) | (u32::from(val) << 8))
         }
         /// ECC PKEY is a valid destination

hw/latest/registers/src/mbox.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -87,13 +87,13 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
-    /// Stores the AXI ID that locked the mailbox
+    /// Stores the AXI USER that locked the mailbox
     /// [br]Caliptra Access: RO
     /// [br]SOC Access:      RO
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
-    pub fn id(&self) -> ureg::RegRef<crate::mbox::meta::Id, &TMmio> {
+    pub fn user(&self) -> ureg::RegRef<crate::mbox::meta::User, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
                 self.ptr.wrapping_add(4 / core::mem::size_of::<u32>()),
@@ -118,7 +118,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     /// Data length for mailbox access in bytes
     /// [br]Caliptra Access: RW
     /// [br]SOC Access:      RW
-    /// [br]TAP Access [in debug/manuf mode]: RO
+    /// [br]TAP Access [in debug/manuf mode]: RW
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
@@ -133,6 +133,7 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
     /// Data in register, write the next data to mailbox
     /// [br]Caliptra Access: RW
     /// [br]SOC Access:      RW
+    /// [br]TAP Access [in debug/manuf mode]: WO
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
@@ -199,6 +200,20 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
+    /// Capability for uC to enable TAP logic to respond to mailbox commands.
+    /// [br]Caliptra Access: RW
+    /// [br]SOC Access:      RO
+    ///
+    /// Read value: [`mbox::regs::TapModeReadVal`]; Write value: [`mbox::regs::TapModeWriteVal`]
+    #[inline(always)]
+    pub fn tap_mode(&self) -> ureg::RegRef<crate::mbox::meta::TapMode, &TMmio> {
+        unsafe {
+            ureg::RegRef::new_with_mmio(
+                self.ptr.wrapping_add(0x24 / core::mem::size_of::<u32>()),
+                core::borrow::Borrow::borrow(&self.mmio),
+            )
+        }
+    }
 }
 pub mod regs {
     //! Types that represent the values held by registers.
@@ -376,6 +391,53 @@ pub mod regs {
         }
     }
     #[derive(Clone, Copy)]
+    pub struct TapModeReadVal(u32);
+    impl TapModeReadVal {
+        ///
+        #[inline(always)]
+        pub fn enabled(&self) -> bool {
+            ((self.0 >> 0) & 1) != 0
+        }
+        /// Construct a WriteVal that can be used to modify the contents of this register value.
+        #[inline(always)]
+        pub fn modify(self) -> TapModeWriteVal {
+            TapModeWriteVal(self.0)
+        }
+    }
+    impl From<u32> for TapModeReadVal {
+        #[inline(always)]
+        fn from(val: u32) -> Self {
+            Self(val)
+        }
+    }
+    impl From<TapModeReadVal> for u32 {
+        #[inline(always)]
+        fn from(val: TapModeReadVal) -> u32 {
+            val.0
+        }
+    }
+    #[derive(Clone, Copy)]
+    pub struct TapModeWriteVal(u32);
+    impl TapModeWriteVal {
+        ///
+        #[inline(always)]
+        pub fn enabled(self, val: bool) -> Self {
+            Self((self.0 & !(1 << 0)) | (u32::from(val) << 0))
+        }
+    }
+    impl From<u32> for TapModeWriteVal {
+        #[inline(always)]
+        fn from(val: u32) -> Self {
+            Self(val)
+        }
+    }
+    impl From<TapModeWriteVal> for u32 {
+        #[inline(always)]
+        fn from(val: TapModeWriteVal) -> u32 {
+            val.0
+        }
+    }
+    #[derive(Clone, Copy)]
     pub struct UnlockReadVal(u32);
     impl UnlockReadVal {
         ///
@@ -593,7 +655,7 @@ pub mod enums {
 pub mod meta {
     //! Additional metadata needed by ureg.
     pub type Lock = ureg::ReadOnlyReg32<crate::mbox::regs::LockReadVal>;
-    pub type Id = ureg::ReadOnlyReg32<u32>;
+    pub type User = ureg::ReadOnlyReg32<u32>;
     pub type Cmd = ureg::ReadWriteReg32<0, u32, u32>;
     pub type Dlen = ureg::ReadWriteReg32<0, u32, u32>;
     pub type Datain = ureg::ReadWriteReg32<0, u32, u32>;
@@ -613,4 +675,9 @@ pub mod meta {
         crate::mbox::regs::UnlockReadVal,
         crate::mbox::regs::UnlockWriteVal,
     >;
+    pub type TapMode = ureg::ReadWriteReg32<
+        0,
+        crate::mbox::regs::TapModeReadVal,
+        crate::mbox::regs::TapModeWriteVal,
+    >;
 }

hw/latest/registers/src/mbox_sram.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/mldsa.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/pv.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/sha256.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/sha512.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]

hw/latest/registers/src/sha512_acc.rs

@@ -1,6 +1,6 @@
 // Licensed under the Apache-2.0 license.
 //
-// generated by caliptra_registers_generator with caliptra-rtl repo at ac8e5592b1a6d53f92809c98f8f0144c5a5bf0eb
+// generated by caliptra_registers_generator with caliptra-rtl repo at 00730026cdf11841d20a6085ea3909ea3bd4a21b
 //
 #![allow(clippy::erasing_op)]
 #![allow(clippy::identity_op)]
@@ -87,13 +87,13 @@ impl<TMmio: ureg::Mmio> RegisterBlock<TMmio> {
             )
         }
     }
-    /// Stores the AXI ID that locked the SHA
+    /// Stores the AXI USER that locked the SHA
     /// [br]Caliptra Access: RO
     /// [br]SOC Access:      RO
     ///
     /// Read value: [`u32`]; Write value: [`u32`]
     #[inline(always)]
-    pub fn id(&self) -> ureg::RegRef<crate::sha512_acc::meta::Id, &TMmio> {
+    pub fn user(&self) -> ureg::RegRef<crate::sha512_acc::meta::User, &TMmio> {
         unsafe {
             ureg::RegRef::new_with_mmio(
                 self.ptr.wrapping_add(4 / core::mem::size_of::<u32>()),
@@ -1398,7 +1398,7 @@ pub mod meta {
         crate::sha512_acc::regs::LockReadVal,
         crate::sha512_acc::regs::LockWriteVal,
     >;
-    pub type Id = ureg::ReadOnlyReg32<u32>;
+    pub type User = ureg::ReadOnlyReg32<u32>;
     pub type Mode = ureg::ReadWriteReg32<
         0,
         crate::sha512_acc::regs::ModeReadVal,