Emit FIRRTL bulk connects even for "input" wires (#4219) (#4235)

(cherry picked from commit 0a3d157)

Co-authored-by: Jack Koenig <koenig@sifive.com>

core/src/main/scala/chisel3/internal/MonoConnect.scala

@@ -296,7 +296,7 @@ private[chisel3] object MonoConnect {
 
     // CASE: Context is same module that both sink node and source node are in
     if ((context_mod == sink_mod) && (context_mod == source_mod)) {
-      sink.direction != Input
+      !sink_is_port || sink.direction != Input
     }
 
     // CASE: Context is same module as sink node and source node is in a child module

src/test/scala/chiselTests/BulkConnectSpec.scala

@@ -112,4 +112,15 @@ class BulkConnectSpec extends ChiselPropSpec {
     chirrtl should include("connect out1[0], in1[1]")
     chirrtl should include("connect out1[1], in1[0]")
   }
+
+  property("Chisel should emit FIRRTL bulk connect for \"input\" wires") {
+    class MyBundle extends Bundle {
+      val foo = Input(UInt(8.W))
+    }
+    val chirrtl = ChiselStage.emitCHIRRTL(new Module {
+      val w1, w2 = Wire(new MyBundle)
+      w2 <> w1
+    })
+    chirrtl should include("connect w2, w1")
+  }
 }