Support Property in BoringUtils. (#3784) (#3791)

This adds support for BoringUtils.bore to bore and connect Property
ports.

(cherry picked from commit 178d8f0)

Co-authored-by: Mike Urbach <mike.urbach@sifive.com>

core/src/main/scala/chisel3/RawModule.scala

@@ -7,7 +7,7 @@ import scala.language.experimental.macros
 import chisel3.experimental.{BaseModule, SourceInfo, UnlocatableSourceInfo}
 import chisel3.internal._
 import chisel3.experimental.hierarchy.{InstanceClone, ModuleClone}
-import chisel3.properties.{DynamicObject, StaticObject}
+import chisel3.properties.{DynamicObject, Property, StaticObject}
 import chisel3.internal.Builder._
 import chisel3.internal.firrtl.ir._
 import _root_.firrtl.annotations.{IsModule, ModuleTarget}
@@ -205,7 +205,11 @@ abstract class RawModule extends BaseModule {
       case (true, false) if left.probeInfo.get.writable => ProbeDefine(si, left.lref, RWProbeExpr(Node(right)))
       case (true, false)                                => ProbeDefine(si, left.lref, ProbeExpr(Node(right)))
       case (false, true)                                => Connect(si, left.lref, ProbeRead(Node(right)))
-      case (false, false)                               => Connect(si, left.lref, Node(right))
+      case (false, false) =>
+        (left, right) match {
+          case (_: Property[_], _: Property[_]) => PropAssign(si, left.lref, Node(right))
+          case (_, _) => Connect(si, left.lref, Node(right))
+        }
     }
     val secretCommands = if (_closed) {
       _component.get.asInstanceOf[DefModule].secretCommands

src/main/scala/chisel3/util/experimental/BoringUtils.scala

@@ -288,7 +288,10 @@ object BoringUtils {
     val lcaSource = drill(source, upPath.dropRight(1), upPath.dropRight(1), true)
     val sink = drill(lcaSource, downPath.reverse.tail, downPath.reverse, false)
 
-    if (createProbe.nonEmpty || DataMirror.hasProbeTypeModifier(purePortTypeBase)) {
+    if (
+      createProbe.nonEmpty || DataMirror.hasProbeTypeModifier(purePortTypeBase) ||
+      DataMirror.isProperty(purePortTypeBase)
+    ) {
       sink
     } else {
       // Creating a wire to assign the result to.  We will return this.

src/test/scala/chiselTests/BoringUtilsSpec.scala

@@ -7,6 +7,7 @@ import chisel3.util.Counter
 import chisel3.testers._
 import chisel3.experimental.{BaseModule, ChiselAnnotation}
 import chisel3.probe._
+import chisel3.properties.Property
 import chisel3.util.experimental.BoringUtils
 import firrtl.annotations.Annotation
 import firrtl.transforms.DontTouchAnnotation
@@ -349,4 +350,30 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners with Utils with
       "connect a_bore, a"
     )
   }
+
+  it should "bore from a Property" in {
+    class Baz extends RawModule {
+      val a = IO(Output(Property[Int]()))
+    }
+
+    class Bar extends RawModule {
+      val baz = Module(new Baz)
+    }
+
+    class Foo extends RawModule {
+      val a = IO(Output(Property[Int]()))
+
+      val bar = Module(new Bar)
+
+      a := BoringUtils.bore(bar.baz.a)
+    }
+
+    val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)
+
+    matchesAndOmits(chirrtl)(
+      "output a_bore : Integer",
+      "propassign a_bore, baz.a",
+      "propassign a, bar.a_bore"
+    )()
+  }
 }