[SVSim] Fixed non-firing AssertProperty in SVSim (#4087)

chipsalliance · May 23, 2024 · d3ab477 · d3ab477
1 parent 5af27e5
commit d3ab477
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Showing 2 changed files with 11 additions and 1 deletion.
diff --git a/src/test/scala/chiselTests/LTLSpec.scala b/src/test/scala/chiselTests/LTLSpec.scala
@@ -7,13 +7,14 @@ import chisel3.ltl._
 import chisel3.testers.BasicTester
 import chisel3.experimental.SourceLine
 import _root_.circt.stage.ChiselStage
+import chiselTests.ChiselRunners
 
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
 import Sequence._
 
-class LTLSpec extends AnyFlatSpec with Matchers {
+class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
   it should "allow booleans to be used as sequences" in {
     val chirrtl = ChiselStage.emitCHIRRTL(new RawModule {
       val a = IO(Input(Bool()))
@@ -317,4 +318,12 @@ class LTLSpec extends AnyFlatSpec with Matchers {
   it should "compile Sequence(...) convenience constructor" in {
     ChiselStage.emitSystemVerilog(new SequenceConvMod)
   }
+
+  it should "fail correctly in verilator simulation" in {
+    assertTesterFails(new BasicTester {
+      withClockAndReset(clock, reset) {
+        AssertProperty(0.U === 1.U)
+      }
+    })
+  }
 }
diff --git a/svsim/src/main/scala/verilator/Backend.scala b/svsim/src/main/scala/verilator/Backend.scala
@@ -59,6 +59,7 @@ final class Backend(
             "-o", s"../$outputBinaryName", // "Name of final executable"
             "--top-module", topModuleName, // "Name of top-level input module"
             "--Mdir", "verilated-sources",  // "Name of output object directory"
+            "--assert", // Enable assertions 
           ),
 
           commonSettings.libraryExtensions match {