Are there available DRAM and PCIe modules/libraries in chisel?

[hiratz]

Hi

I'm new to Chisel and am learning how to write an accelerator with chisel on FPGA. The basic framework is that host sends data to FPGA-attached on-board dram via PCIe and then the accelerator reads input from the dram, does calculations and writes the results back to dram. Then some logic module reads results from dram and sends them back to host.

I wonder if there are available DRAM module and PCIe module in chisel? Or users have to write them manually with chisel?

Thank you!

[ekiwi]

What kind of FPGA are you using? I have some experience with Xilinx FPGAs and for those I would recommend writing your custom data processing module in Chisel and then importing that into Vivado where you can then instantiate the Xilinx PCIe and DRAM IPs and connect them to your module. I did something similar-ish here: https://github.com/ekiwi/pynq (not using PCIe or DRAM, but it is a good example for how to integrate a Chisel design into Vivado)

[hiratz]

Hi ekiwi, thank you for quick response!

I've been using Xilinx VC707. Previously, I've been using Bluespec to design accelerators. Besides the accelerator modules (i.e., the data processing module), we also have Bluespec-based dram controller module (DDR3) and PCIe module. Therefore it is easy to achieve the whole host-FPGA framework I mentioned above in Bluespec.

Now I want to learn Chisel. So the immediate needs for achieving a host-FPGA framework is to find a Chisel-based DRAM and PCIe module. So I can finish the whole design with Chisel. Though importing accelerator module into Vivado is a feasible way to connect it with DRAM and PCIe IP, it seems that developers cannot make interaction between the accelerator module and these external IPs, like DRAM on a source-code level. For example, if I want to design a dram arbiter module with multiple ports and let my accelerator access this arbiter using some logic, I cannot do it without accessing the dram module's chisel source code (Please correct me if I am wrong).

Thanks for sharing that useful link! I'll take a look at it.

Happy New Year

[ekiwi]

With bluespec, are you using this library? https://github.com/sangwoojun/bluespecpcie

[ekiwi]

There are Chisel libraries that wrap Xilinx IP, most notably https://github.com/sifive/fpga-shells which is focused on CPU prototyping for local FPGAs.

[hiratz]

Yes, I use the bluespecpcie repository.

Thanks for sharing the fpga-shells repository! I looked at some code and they are indeed the wrappers instead of the actual implementation. Right now I'm not sure if I can use them to implement some functions I can do with the bluespecpcie because I still need some time to make myself familiarize with the Chisel/Scala grammar. Take the above-mentioned dram arbiter for example, I think I can write a chisel dram-arbiter module as long as there is a underlying chisel dram controller (or wrapper) that provides necessary interfaces like read_request/read/write.