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Implement DecoupledIO.map utility #2646

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merged 11 commits into from
Jul 28, 2022
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jared-barocsi
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Addresses #1072: Implements a new utility for Decoupled which applies a function to its data.

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Type of Improvement

  • new feature/API

API Impact

  • Adds Decoupled.map to apply a function to a DecoupledIO and return the new resulting DecoupledIO

Backend Code Generation Impact

  • No change to verilog

Desired Merge Strategy

  • Squash and merge

Release Notes

Implement DecoupledIO.map to apply a function to DecoupledIO.bits

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implicit class DecoupledExtensions[A <: Data](x: DecoupledIO[A]) {
def map[B <: Data](f: A => B): DecoupledIO[B] = {
val res = f(x.bits)
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What if this were called "bits" and wire was called "res"? Just looking at the names of the resulting signals

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Or "res_bits" and "res"

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@jackkoenig jackkoenig Jul 27, 2022

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Alternatively, it could just be wire.bits := f(x.bits), or I think I like map better as a name because it indicates that this came from calling .map.

Also, this might be a good opportunity to utilize #2580 by using _ as the leading character for names in this block (wire in particular isn't a super useful name in the Verilog, but map could be...).

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Use of the leading underscore seems good to me. Maybe _map or _mapped. Alternatively, don't create a val res here and just inline it. That'll create an unnamed node and that should get inlined? That would then motivate changing val wire to val _map.

Can you generate some examples of what the output looks like in Verilog for this?

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@hcook hcook left a comment

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Looking forward to using this.

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@jackkoenig jackkoenig left a comment

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Minor suggestions for improvements to the tests, but otherwise, this looks great!

src/test/scala/chiselTests/DecoupledSpec.scala Outdated Show resolved Hide resolved
src/test/scala/chiselTests/DecoupledSpec.scala Outdated Show resolved Hide resolved
src/test/scala/chiselTests/DecoupledSpec.scala Outdated Show resolved Hide resolved
@jackkoenig jackkoenig added this to the 3.5.x milestone Jul 28, 2022
@jackkoenig jackkoenig enabled auto-merge (squash) July 28, 2022 21:03
@jackkoenig jackkoenig added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Jul 28, 2022
@jackkoenig jackkoenig merged commit b20df1d into chipsalliance:master Jul 28, 2022
mergify bot pushed a commit that referenced this pull request Jul 28, 2022
@mergify mergify bot added the Backported This PR has been backported label Jul 28, 2022
mergify bot added a commit that referenced this pull request Jul 28, 2022
(cherry picked from commit b20df1d)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
@tymcauley tymcauley mentioned this pull request Jul 9, 2024
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@mergify mergify bot mentioned this pull request Jul 9, 2024
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6 participants