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Fix Reg() to properly handle clocks as rvalues (backport #3775) #3779

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merged 4 commits into from
Jan 30, 2024

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@mergify mergify bot commented Jan 29, 2024

This is an automatic backport of pull request #3775 done by Mergify.
Cherry-pick of 1c348c5 has failed:

On branch mergify/bp/5.x/pr-3775
Your branch is up to date with 'origin/5.x'.

You are currently cherry-picking commit 1c348c558.
  (fix conflicts and run "git cherry-pick --continue")
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  (use "git cherry-pick --abort" to cancel the cherry-pick operation)

Changes to be committed:
	modified:   core/src/main/scala/chisel3/Reg.scala

Unmerged paths:
  (use "git add/rm <file>..." as appropriate to mark resolution)
	deleted by us:   src/test/scala/chiselTests/ClockSpec.scala

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Original PR Body

Previously, it was not calling .ref. It was thus not properly:

  1. Checking that the clock is bound hardware
  2. Checking that the clock is visible in the current scope
  3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

h/t @nandor for noticing this, pretty crazy such a fundamental bug has been lingering without being noticed.

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Bugfix

Desired Merge Strategy

  • Squash

Release Notes

  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
  • Did you review?
  • Did you check whether all relevant Contributor checkboxes have been checked?
  • Did you do one of the following when ready to merge:
    • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
    • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

Previously, it was not calling .ref. It was thus not properly:
1. Checking that the clock is bound hardware
2. Checking that the clock is visible in the current scope
3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

(cherry picked from commit 1c348c5)

# Conflicts:
#	src/test/scala/chiselTests/ClockSpec.scala
@mergify mergify bot added Backport Automated backport, please consider for minor release bp-conflict labels Jan 29, 2024
@github-actions github-actions bot added the Bugfix Fixes a bug, will be included in release notes label Jan 29, 2024
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linux-foundation-easycla bot commented Jan 30, 2024

CLA Signed

The committers listed above are authorized under a signed CLA.

@jackkoenig jackkoenig force-pushed the mergify/bp/5.x/pr-3775 branch 2 times, most recently from b02bd59 to 8d06d7a Compare January 30, 2024 22:22
@chiselbot chiselbot merged commit 4515965 into 5.x Jan 30, 2024
17 checks passed
@chiselbot chiselbot deleted the mergify/bp/5.x/pr-3775 branch January 30, 2024 22:51
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