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Make SRAMInterface parameters publicly available (backport #3826) #3828

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Feb 16, 2024
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Make SRAMInterface parameters publicly available (backport #3826) #3828

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17 changes: 11 additions & 6 deletions src/main/scala/chisel3/util/SRAM.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -82,13 +82,18 @@ class MemoryReadWritePort[T <: Data](tpe: T, addrWidth: Int, masked: Boolean) ex
* @param masked Whether the memory is write masked
*/
class SRAMInterface[T <: Data](
memSize: BigInt,
tpe: T,
numReadPorts: Int,
numWritePorts: Int,
numReadwritePorts: Int,
masked: Boolean = false)
val memSize: BigInt,
// tpe can't be directly made public as it will become a Bundle field
tpe: T,
val numReadPorts: Int,
val numWritePorts: Int,
val numReadwritePorts: Int,
val masked: Boolean = false)
extends Bundle {

/** Public accessor for data type of this interface. */
def dataType: T = tpe

if (masked) {
require(
tpe.isInstanceOf[Vec[_]],
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