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Remove extra bit from SRAMInterface address width #3830

Merged
merged 3 commits into from
Feb 20, 2024
Merged

Remove extra bit from SRAMInterface address width #3830

merged 3 commits into from
Feb 20, 2024

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debs-sifive
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Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Bugfix

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
  • Did you review?
  • Did you check whether all relevant Contributor checkboxes have been checked?
  • Did you do one of the following when ready to merge:
    • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
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@jackkoenig jackkoenig added the Bugfix Fixes a bug, will be included in release notes label Feb 16, 2024
@jackkoenig jackkoenig added this to the 3.6.x milestone Feb 16, 2024
jackkoenig
jackkoenig approved these changes Feb 16, 2024
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lol this test should've tipped us off originally 🙈

@sequencer
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I debugged one of strange SRAM behavior for 2 days last week

@debs-sifive debs-sifive merged commit 4f1f4a7 into main Feb 20, 2024
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@debs-sifive debs-sifive deleted the debs-sifive/addrwidth-fix branch February 20, 2024 16:34
@mergify mergify bot added the Backported This PR has been backported label Feb 20, 2024
mergify bot pushed a commit that referenced this pull request Feb 20, 2024
@debs-sifive @mergify
Remove extra bit from SRAMInterface address width (#3830)
80831d6 
(cherry picked from commit 4f1f4a7)
mergify bot pushed a commit that referenced this pull request Feb 20, 2024
@debs-sifive @mergify
Remove extra bit from SRAMInterface address width (#3830)
fb6e4b0 
(cherry picked from commit 4f1f4a7)

# Conflicts:
#	src/test/scala/chiselTests/util/SRAMSpec.scala
mergify bot pushed a commit that referenced this pull request Feb 20, 2024
@debs-sifive @mergify
Remove extra bit from SRAMInterface address width (#3830)
bda062c 
(cherry picked from commit 4f1f4a7)

# Conflicts:
#	src/test/scala/chiselTests/Mem.scala
#	src/test/scala/chiselTests/util/SRAMSpec.scala
This was referenced Feb 20, 2024
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chiselbot pushed a commit that referenced this pull request Feb 20, 2024
@mergify @debs-sifive
Remove extra bit from SRAMInterface address width (#3830) (#3840)
ff01f70 
(cherry picked from commit 4f1f4a7)

Co-authored-by: Deborah Soung <debs@sifive.com>
sequencer pushed a commit that referenced this pull request Feb 28, 2024
@debs-sifive @sequencer
Remove extra bit from SRAMInterface address width (#3830)
f007720
chiselbot pushed a commit that referenced this pull request Apr 18, 2024
@mergify @debs-sifive @jackkoenig
Remove extra bit from SRAMInterface address width (backport #3830) (#…
ac3d7e2 
…3839)

* Remove extra bit from `SRAMInterface` address width (#3830)

(cherry picked from commit 4f1f4a7)

# Conflicts:
#	src/test/scala/chiselTests/util/SRAMSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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