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Allow BoringUtils.bore to work on probes #3908

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merged 2 commits into from
Mar 6, 2024
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Allow BoringUtils.bore to work on probes #3908

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f0e4c14
Allow BoringUtils.bore to work on probes
seldridge Mar 6, 2024
2916ca3
fixup! Allow BoringUtils.bore to work on probes
seldridge Mar 6, 2024
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11 changes: 8 additions & 3 deletions src/main/scala/chisel3/util/experimental/BoringUtils.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -224,9 +224,14 @@ object BoringUtils {
else if (DataMirror.hasOuterFlip(source)) Flipped(chiselTypeOf(source))
else chiselTypeOf(source)
def purePortType = createProbe match {
case Some(pi) if pi.writable => RWProbe(purePortTypeBase)
case Some(pi) => Probe(purePortTypeBase)
case None => purePortTypeBase
case Some(pi) =>
// If the source is already a probe, don't double wrap it in a probe.
purePortTypeBase.probeInfo match {
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Things get strange if the bore/tap target is mixed probe/non-probe, but that's already true.

(or if has incompatible probe type vs requested kind)

Not sure what the errors look like if this is wrong.

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Not something to be addressed here unless it seems easy/reasonable to address while visiting (?), just a note.

case Some(_) => purePortTypeBase
case None if pi.writable => RWProbe(purePortTypeBase)
case None => Probe(purePortTypeBase)
}
case None => purePortTypeBase
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Some of the below logic maybe can/should be tweaked, not sure and maybe better to defer that to a later simplification.
For example, if the target is a rwprobe port (new L251, old L246), and this is used by rwTap, it'll add another RWProbe for that. Possibly error but haven't traced all the paths here...

}
def isPort(d: Data): Boolean = d.topBindingOpt match {
case Some(PortBinding(_)) => true
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17 changes: 17 additions & 0 deletions src/test/scala/chiselTests/BoringUtilsTapSpec.scala
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Expand Up @@ -495,4 +495,21 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
val verilog = circt.stage.ChiselStage.emitSystemVerilog(new Foo)
}

it should "allow tapping a probe" in {
class Bar extends RawModule {
val a = IO(probe.Probe(Bool()))
}
class Foo extends RawModule {
val b = IO(probe.Probe(Bool()))
val bar = Module(new Bar)
probe.define(b, BoringUtils.tap(bar.a))
}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo)

matchesAndOmits(chirrtl)(
"define b = bar.a"
)()
}

}
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