Add modulePorts and fullModulePorts in DataMirror for Instance (backport #4076)

core/src/main/scala/chisel3/reflect/DataMirror.scala

@@ -6,6 +6,7 @@ import chisel3._
 import chisel3.internal._
 import chisel3.internal.firrtl.ir._
 import chisel3.experimental.{requireIsHardware, BaseModule, SourceInfo}
+import chisel3.experimental.hierarchy.Instance
 import chisel3.properties.Property
 import scala.reflect.ClassTag
 
@@ -143,6 +144,15 @@ object DataMirror {
     case (name, port: Data) => (name, port)
   }
 
+  /** Returns the ports of a `chisel3.experimental.hierarchy.Instance` of a module
+    */
+  def modulePorts[T <: BaseModule](inst: Instance[T])(implicit si: SourceInfo): Seq[(String, Data)] = {
+    // This prevents users from using the _lookup API
+    implicit val mg = new chisel3.internal.MacroGenerated {}
+
+    inst._lookup { proto: T => modulePorts(proto) }
+  }
+
   /** Returns a recursive representation of a module's ports with underscore-qualified names
     * {{{
     * class MyModule extends Module {
@@ -170,7 +180,7 @@ object DataMirror {
     * }}}
     * @note The returned ports are redundant. An [[Aggregate]] port will be present along with all
     *       of its children.
-    * @see [[DataMirror.modulePorts]] for a non-recursive representation of the ports.
+    * @see `DataMirror.modulePorts` for a non-recursive representation of the ports.
     */
   def fullModulePorts(target: BaseModule)(implicit si: SourceInfo): Seq[(String, Data)] = {
     def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match {
@@ -189,6 +199,20 @@ object DataMirror {
     }
   }
 
+  /** Returns a recursive representation of an `chisel3.experimental.hierarchy.Instance` of a
+    * module's ports with underscore-qualified names.
+    *
+    * @note The returned ports are redundant. An [[Aggregate]] port will be present along with all
+    *       of its children.
+    * @see `DataMirror.modulePorts` for a non-recursive representation of the ports.
+    */
+  def fullModulePorts[T <: BaseModule](inst: Instance[T])(implicit si: SourceInfo): Seq[(String, Data)] = {
+    // This prevents users from using the _lookup API
+    implicit val mg = new chisel3.internal.MacroGenerated {}
+
+    inst._lookup { proto: T => fullModulePorts(proto) }
+  }
+
   /** Returns the parent module within which a module instance is instantiated
     *
     * @note Top-level modules in any given elaboration do not have a parent

src/test/scala/chiselTests/reflect/DataMirrorSpec.scala

@@ -224,4 +224,38 @@ class DataMirrorSpec extends ChiselFlatSpec {
     assert(DataMirror.isFullyAligned(UInt(8.W)))
   }
 
+  "modulePorts and fullModulePorts" should "return an Instance of a module's IOs" in {
+    @instantiable
+    class Bar extends Module {
+      @public val io = IO(new Bundle {
+        val vec = Vec(2, Bool())
+        val x = UInt(4.W)
+      })
+    }
+
+    class Foo extends Module {
+      val definition = Definition(new Bar)
+      val instA = Instance(definition)
+      val portsA = DataMirror.modulePorts(instA)
+
+      val instB = (Module(new Bar)).toInstance
+      val portsB = DataMirror.fullModulePorts(instB)
+    }
+
+    ChiselStage.emitCHIRRTL(new Module {
+      val foo = Module(new Foo)
+      foo.portsA.map(_._1) should be(Seq("clock", "reset", "io"))
+      foo.portsB.map(_._1) should be(
+        Seq(
+          "clock",
+          "reset",
+          "io",
+          "io_x",
+          "io_vec",
+          "io_vec_0",
+          "io_vec_1"
+        )
+      )
+    })
+  }
 }