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Fix boring tap of non-passive source from parent. #4083

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merged 1 commit into from
May 24, 2024
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Fix boring tap of non-passive source from parent. #4083

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7 changes: 7 additions & 0 deletions core/src/main/scala/chisel3/RawModule.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ import chisel3.experimental.hierarchy.{InstanceClone, ModuleClone}
import chisel3.properties.{DynamicObject, Property, StaticObject}
import chisel3.internal.Builder._
import chisel3.internal.firrtl.ir._
import chisel3.reflect.DataMirror
import _root_.firrtl.annotations.{IsModule, ModuleTarget}
import scala.collection.immutable.VectorBuilder
import scala.collection.mutable.ArrayBuffer
Expand Down Expand Up @@ -217,6 +218,12 @@ abstract class RawModule extends BaseModule {
// For non-probe, directly create Nodes for lhs, skipping visibility check to support BoringUtils.drive.
(left, right) match {
case (_: Property[_], _: Property[_]) => PropAssign(si, Node(left), Node(right))
// Use `connect lhs, read(probe(rhs))` if lhs is passive version of rhs.
// This provides solution for this: https://github.com/chipsalliance/chisel/issues/3557
case (_, _)
if !DataMirror.checkAlignmentTypeEquivalence(left, right) &&
DataMirror.checkAlignmentTypeEquivalence(left, Output(chiselTypeOf(right))) =>
Connect(si, Node(left), ProbeRead(ProbeExpr(Node(right))))
case (_, _) => Connect(si, Node(left), Node(right))
}
}
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12 changes: 2 additions & 10 deletions src/test/scala/chiselTests/BoringUtilsTapSpec.scala
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Expand Up @@ -470,13 +470,7 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi

class Foo extends RawModule {
val a = WireInit(DecoupledIO(Bool()), DontCare)
val dummyA = Wire(Output(chiselTypeOf(a)))
// FIXME we shouldn't need this intermediate wire
// https://github.com/chipsalliance/chisel/issues/3557
dummyA :#= a
dontTouch(a)

val bar = Module(new Bar(dummyA))
val bar = Module(new Bar(a))
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}

val chirrtl = circt.stage.ChiselStage.emitCHIRRTL(new Foo, Array("--full-stacktrace"))
Expand All @@ -486,9 +480,7 @@ class BoringUtilsTapSpec extends ChiselFlatSpec with ChiselRunners with Utils wi
"input bore : { ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}",
"module Foo :",
"wire a : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}",
// FIXME shouldn't need intermediate wire
"wire dummyA : { ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}",
"connect bar.bore, dummyA"
"connect bar.bore, read(probe(a))"
)()

// Check that firtool also passes
Expand Down
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