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Fix widths for literal values in Bundle literals (backport #4082) #4091

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merged 2 commits into from
May 24, 2024

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@mergify mergify bot commented May 23, 2024

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
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  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Bugfix

Desired Merge Strategy

  • Squash

Release Notes

Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
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This is an automatic backport of pull request #4082 done by [Mergify](https://mergify.com).

@mergify mergify bot added Backport Automated backport, please consider for minor release bp-conflict labels May 23, 2024
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mergify bot commented May 23, 2024

Cherry-pick of 3939e57 has failed:

On branch mergify/bp/5.x/pr-4082
Your branch is up to date with 'origin/5.x'.

You are currently cherry-picking commit 3939e570d.
  (fix conflicts and run "git cherry-pick --continue")
  (use "git cherry-pick --skip" to skip this patch)
  (use "git cherry-pick --abort" to cancel the cherry-pick operation)

Changes to be committed:
	modified:   core/src/main/scala/chisel3/Aggregate.scala
	modified:   src/test/scala/chiselTests/BundleLiteralSpec.scala

Unmerged paths:
  (use "git add <file>..." to mark resolution)
	both modified:   core/src/main/scala/chisel3/internal/firrtl/IR.scala
	both modified:   src/test/scala/chiselTests/ConnectableSpec.scala
	both modified:   src/test/scala/chiselTests/VecLiteralSpec.scala

To fix up this pull request, you can check it out locally. See documentation: https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/checking-out-pull-requests-locally

@github-actions github-actions bot added the Bugfix Fixes a bug, will be included in release notes label May 23, 2024
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linux-foundation-easycla bot commented May 24, 2024

CLA Signed

The committers listed above are authorized under a signed CLA.

* Fix widths for literal values in Bundle literals

Previously, the user-specified (or unspecified minimum width) of the
literal would be used in some operations like concatenation.

* Implicitly truncate too-wide literals in Bundle literals

This is to fix a bug in concatenation without breaking things relying on
implicit truncation. This will be a warning in newer versions of Chisel.

(cherry picked from commit 3939e57)

# Conflicts:
#	core/src/main/scala/chisel3/internal/firrtl/IR.scala
#	src/test/scala/chiselTests/ConnectableSpec.scala
#	src/test/scala/chiselTests/VecLiteralSpec.scala
Also move waivers from files to build.sbt.
@chiselbot chiselbot merged commit 9b3918e into 5.x May 24, 2024
17 checks passed
@chiselbot chiselbot deleted the mergify/bp/5.x/pr-4082 branch May 24, 2024 00:39
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