Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

add test for FlatIO port ordering #4113

Merged
merged 3 commits into from
May 30, 2024
Merged

add test for FlatIO port ordering #4113

Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
810204e
add test for FlatIO port ordering
mwachs5 May 30, 2024
92ea454
Update src/test/scala/chiselTests/experimental/FlatIOSpec.scala
mwachs5 May 30, 2024
430bcc2
Update src/test/scala/chiselTests/experimental/FlatIOSpec.scala
mwachs5 May 30, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
49 changes: 46 additions & 3 deletions src/test/scala/chiselTests/experimental/FlatIOSpec.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,12 @@ import chisel3._
import chisel3.util.Valid
import circt.stage.ChiselStage.emitCHIRRTL
import chisel3.experimental.Analog
import chiselTests.ChiselFlatSpec
import chiselTests.{ChiselFlatSpec, MatchesAndOmits}
import chisel3.reflect.DataMirror
import scala.collection.immutable.SeqMap
import circt.stage.ChiselStage

class FlatIOSpec extends ChiselFlatSpec {
class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits {
behavior.of("FlatIO")

it should "create ports without a prefix" in {
Expand Down Expand Up @@ -36,7 +39,7 @@ class FlatIOSpec extends ChiselFlatSpec {
chirrtl should include("connect out.valid, valid")
}

it should "dynamically indexing Vecs inside of FlatIOs" in {
it should "support dynamically indexing Vecs inside of FlatIOs" in {
class MyModule extends RawModule {
val io = FlatIO(new Bundle {
val addr = Input(UInt(2.W))
Expand Down Expand Up @@ -76,4 +79,44 @@ class FlatIOSpec extends ChiselFlatSpec {
chirrtl should include("output a : UInt<1>")
chirrtl should include("output b : UInt<2>[2]")
}

it should "maintain port order for Bundles" in {
class MyBundle extends Bundle {
val foo = Bool()
val bar = Bool()
}
class MyModule extends Module {
val io = IO(Input(new MyBundle))
}
class MyFlatIOModule extends Module {
val io = FlatIO(Input(new MyBundle))
}

matchesAndOmits(
ChiselStage.emitSystemVerilog(new MyModule)
)("io_foo,")("io_bar,")

matchesAndOmits(
ChiselStage.emitSystemVerilog(new MyFlatIOModule)
)("foo,")("bar,")
}
Comment on lines +95 to +102
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Clever, I need to just finish and merge #3410 as that would be a good way to test this.

I wonder if we should also check Vec and also check recursive order...


it should "maintain port order for Records" in {
class MyRecord extends Record {
val elements = SeqMap("foo" -> Bool(), "bar" -> Bool())
}
class MyModule extends Module {
val io = IO(Input(new MyRecord))
}
class MyFlatIOModule extends Module {
val io = FlatIO(Input(new MyRecord))
}
matchesAndOmits(
ChiselStage.emitSystemVerilog(new MyModule)
)("io_bar,")("io_foo,")
matchesAndOmits(
ChiselStage.emitSystemVerilog(new MyFlatIOModule)
)("bar,")("foo,")
}

}
Loading