add test for FlatIO port ordering (backport #4113)

[mergify]

This is just a unit test. I thought going into writing the test that FlatIO maybe was not working as we intended, but i think it is just general misunderstanding of how Record and Bundle treat their elements.

This might be more of a test of CIRCT's lowering ABI, but firtool internally considers the port order part of the contract (not just the name of the signals), so check that we are doing what is sane here.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
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Type of Improvement

• Internal or build-related (includes code refactoring/cleanup)

Desired Merge Strategy

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Release Notes

Added a unit test for FlatIO Ordering being maintained

Reviewer Checklist (only modified by reviewer)

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This is an automatic backport of pull request #4113 done by [Mergify](https://mergify.com).