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Use :<>= in VecInit methods instead of := or <> #4248

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Jul 9, 2024
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Use :<>= in VecInit methods instead of := or <> #4248

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35 changes: 6 additions & 29 deletions core/src/main/scala/chisel3/Aggregate.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -661,26 +661,6 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend

object VecInit extends SourceInfoDoc {

/** Gets the correct connect operation (directed hardware assign or bulk connect) for element in Vec.
*/
private def getConnectOpFromDirectionality[T <: Data](
proto: T
)(
implicit sourceInfo: SourceInfo
): (T, T) => Unit = proto.direction match {
case ActualDirection.Input | ActualDirection.Output | ActualDirection.Unspecified =>
// When internal wires are involved, driver / sink must be specified explicitly, otherwise
// the system is unable to infer which is driver / sink
(x, y) => x := y
case ActualDirection.Bidirectional(_) =>
// For bidirectional, must issue a bulk connect so subelements are resolved correctly.
// Bulk connecting two wires may not succeed because Chisel frontend does not infer
// directions.
(x, y) => x <> y
case ActualDirection.Empty =>
(x, y) => x <> y
}

/** Creates a new [[Vec]] composed of elements of the input Seq of [[Data]]
* nodes.
*
Expand All @@ -706,10 +686,9 @@ object VecInit extends SourceInfoDoc {
elts.foreach(requireIsHardware(_, "vec element"))

val vec = Wire(Vec(elts.length, cloneSupertype(elts, "Vec")))
val op = getConnectOpFromDirectionality(vec.head)

(vec.zip(elts)).foreach { x =>
op(x._1, x._2)
for ((lhs, rhs) <- vec.zip(elts)) {
lhs :<>= rhs
}
vec
}
Expand Down Expand Up @@ -775,12 +754,11 @@ object VecInit extends SourceInfoDoc {

val tpe = cloneSupertype(flatElts, "Vec.tabulate")
val myVec = Wire(Vec(n, Vec(m, tpe)))
val op = getConnectOpFromDirectionality(myVec.head.head)
for {
(xs1D, ys1D) <- myVec.zip(elts)
(x, y) <- xs1D.zip(ys1D)
(lhs, rhs) <- xs1D.zip(ys1D)
} {
op(x, y)
lhs :<>= rhs
}
myVec
}
Expand Down Expand Up @@ -815,14 +793,13 @@ object VecInit extends SourceInfoDoc {

val tpe = cloneSupertype(flatElts, "Vec.tabulate")
val myVec = Wire(Vec(n, Vec(m, Vec(p, tpe))))
val op = getConnectOpFromDirectionality(myVec.head.head.head)

for {
(xs2D, ys2D) <- myVec.zip(elts)
(xs1D, ys1D) <- xs2D.zip(ys2D)
(x, y) <- xs1D.zip(ys1D)
(lhs, rhs) <- xs1D.zip(ys1D)
} {
op(x, y)
lhs :<>= rhs
}

myVec
Expand Down
15 changes: 15 additions & 0 deletions src/test/scala/chiselTests/Vec.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -285,6 +285,21 @@ class VecSpec extends ChiselPropSpec with Utils {
}
}

property("VecInit should work for Bundle that mixes Output and unspecified UInts") {
class MyBundle extends Bundle {
val a = Output(UInt(8.W))
val b = UInt(8.W)
}
val chirrtl = emitCHIRRTL(new RawModule {
val w = VecInit(Seq.fill(2)(0.U.asTypeOf(new MyBundle)))
})
chirrtl should include("wire w : { a : UInt<8>, b : UInt<8>}[2]")
chirrtl should include("connect w[0].b, UInt<8>(0h0)")
chirrtl should include("connect w[0].a, UInt<8>(0h0)")
chirrtl should include("connect w[1].b, UInt<8>(0h0)")
chirrtl should include("connect w[1].a, UInt<8>(0h0)")
}

property("Infering widths on huge Vecs should not cause a stack overflow") {
ChiselStage.emitSystemVerilog(new HugeVecTester(10000))
}
Expand Down