work around bug

chipsalliance · Jan 26, 2022 · 2376492 · 2376492
1 parent 6bf257d
commit 2376492
Showing 1 changed file with 8 additions and 2 deletions.
diff --git a/src/main/scala/rocket/Decode.scala b/src/main/scala/rocket/Decode.scala
@@ -9,8 +9,14 @@ import scala.collection.mutable.ArrayBuffer
 
 object DecodeLogic
 {
-	def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
-    chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping.toMap, default))
+  def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = {
+   try{
+     chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping.toMap, default))
+    } catch {
+     case s: IllegalArgumentException if s.getMessage.contains("TruthTable cannot be empty.") =>
+       0.U
+   }
+  }
   def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
     val mapping = ArrayBuffer.fill(default.size)(ArrayBuffer[(BitPat, BitPat)]())
     for ((key, values) <- mappingIn)