Update src/main/scala/tile/Interrupts.scala

chipsalliance · Apr 25, 2020 · 2c9e91b · 2c9e91b
1 parent 4d762a4
commit 2c9e91b
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala
@@ -106,7 +106,7 @@ trait SourcesExternalNotifications { this: BaseTile =>
       val cease = (waitForQuiescence(c))
       // Test-Only Code --
       val prev_cease = RegNext(c, false.B)
-      assert((!(prev_cease & !c) | reset.asBool), "CEASE line can not glitch once raised") 
+      assert(!(prev_cease & !c), "CEASE line can not glitch once raised") 
       cease
     }.getOrElse(false.B)
   }