Merge pull request #2276 from chipsalliance/chisel3-width-widget

TLWidthWidget: one more fix for the port to chisel3
chipsalliance · Feb 4, 2020 · 36d87ef · 36d87ef
2 parents 5e3ce59 + c0bb78b
commit 36d87ef
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala
@@ -188,7 +188,9 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
       if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
         splice(edgeOut, out.b, edgeIn,  in.b,  sourceMap)
         splice(edgeIn,  in.c,  edgeOut, out.c, sourceMap)
-        out.e <> in.e
+        out.e.valid := in.e.valid
+        out.e.bits := in.e.bits
+        in.e.ready := out.e.ready
       } else {
         in.b.valid := false.B
         in.c.ready := true.B