Fix a DTIM X-prop issue (#2822)

* Fix a DTIM X-prop issue

Convert PutPartials to PutFulls when the mask is full to avoid RMW.

* Rework ScratchpadSlavePort fix, since it dovetails with DTIM fix

Co-authored-by: Andrew Waterman <andrew@sifive.com>

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -71,6 +71,17 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
           TLAtomics.AND           -> M_XA_AND,
           TLAtomics.SWAP          -> M_XA_SWAP)),
         TLMessages.Get            -> M_XRD))
+
+      // Convert full PutPartial into PutFull to work around RMWs causing X-prop problems.
+      // Also prevent cmd becoming X out of reset by checking for s_init.
+      val mask_full = {
+        val desired_mask = new StoreGen(a.size, a.address, 0.U, coreDataBytes).mask
+        (a.mask | ~desired_mask).andR
+      }
+      when (state === s_init || (a.opcode === TLMessages.PutPartialData && mask_full)) {
+        req.cmd := M_XWR
+      }
+
       req.size := a.size
       req.signed := false
       req.addr := a.address
@@ -91,7 +102,6 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
     io.dmem.req.valid := dmem_req_valid_likely
     tl_in.a.ready := io.dmem.req.ready && ready
     io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))
-    when (state === s_init) { io.dmem.req.bits.cmd := M_XRD } // To fix an X-pessimism problem, don't let cmd become X
     io.dmem.s1_data.data := acq.data
     io.dmem.s1_data.mask := acq.mask
     io.dmem.s1_kill := state =/= s_wait1