Merge pull request #2367 from chipsalliance/fix-no-alloc

Fix D$ elaboration with < 4 MiB of physical address space
chipsalliance · Mar 26, 2020 · 91a4873 · 91a4873
2 parents 2f6c749 + 4cc8686
commit 91a4873
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Showing 2 changed files with 10 additions and 27 deletions.
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
@@ -344,7 +344,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
   val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
   val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit
-  val s2_no_alloc_hazard = {
+  val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else {
     // make sure that any in-flight non-allocating accesses are ordered before
     // any allocating accesses.  this can only happen if aliasing is possible.
     val any_no_alloc_in_flight = Reg(Bool())
@@ -362,8 +362,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     }
 
     val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked)
-
-    usingVM && pgIdxBits < untagBits && s2_uncached_hits.orR
+    s2_uncached_hits.orR
   }
   val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard
   val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line

diff --git a/src/main/scala/util/AsyncQueue.scala b/src/main/scala/util/AsyncQueue.scala
@@ -55,16 +55,12 @@ object GrayCounter {
   }
 }
 
-class AsyncValidSync(sync: Int, desc: String) extends RawModule {
+class AsyncValidSync(sync: Int, desc: String) extends Module {
   val io = IO(new Bundle {
     val in = Input(Bool())
     val out = Output(Bool())
   })
-  val clock = IO(Input(Clock()))
-  val reset = IO(Input(AsyncReset()))
-  withClockAndReset(clock, reset){
-    io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
-  }
+  io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
 }
 
 class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
@@ -102,15 +98,9 @@ class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueP
 
     val sink_extend  = Module(new AsyncValidSync(params.sync, "sink_extend"))
     val sink_valid   = Module(new AsyncValidSync(params.sync, "sink_valid"))
-    source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
-    source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
-    sink_extend   .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
-    sink_valid    .reset := reset.asAsyncReset
-
-    source_valid_0.clock := clock
-    source_valid_1.clock := clock
-    sink_extend   .clock := clock
-    sink_valid    .clock := clock
+    source_valid_0.reset := reset.asBool || !sio.sink_reset_n
+    source_valid_1.reset := reset.asBool || !sio.sink_reset_n
+    sink_extend   .reset := reset.asBool || !sio.sink_reset_n
 
     source_valid_0.io.in := true.B
     source_valid_1.io.in := source_valid_0.io.out
@@ -170,15 +160,9 @@ class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueuePar
 
     val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
     val source_valid  = Module(new AsyncValidSync(params.sync, "source_valid"))
-    sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
-    sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
-    source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
-    source_valid .reset := reset.asAsyncReset
-
-    sink_valid_0 .clock := clock
-    sink_valid_1 .clock := clock
-    source_extend.clock := clock
-    source_valid .clock := clock
+    sink_valid_0 .reset := reset.asBool || !sio.source_reset_n
+    sink_valid_1 .reset := reset.asBool || !sio.source_reset_n
+    source_extend.reset := reset.asBool || !sio.source_reset_n
 
     sink_valid_0.io.in := true.B
     sink_valid_1.io.in := sink_valid_0.io.out