work around bug

chipsalliance · Jan 24, 2022 · 9d22607 · 9d22607
1 parent 6bf257d
commit 9d22607
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/src/main/scala/rocket/Decode.scala b/src/main/scala/rocket/Decode.scala
@@ -9,8 +9,11 @@ import scala.collection.mutable.ArrayBuffer
 
 object DecodeLogic
 {
-	def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
-    chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping.toMap, default))
+	def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = {
+    if (mapping.nonEmpty)
+      chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping.toMap, default))
+    else 0.U
+  }
   def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
     val mapping = ArrayBuffer.fill(default.size)(ArrayBuffer[(BitPat, BitPat)]())
     for ((key, values) <- mappingIn)