axi4: change AXID to A[W|R]ID in scaladoc

chipsalliance · Oct 26, 2020 · c5db42d · c5db42d
1 parent 5362005
commit c5db42d
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala
@@ -16,7 +16,7 @@ case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(U
   * which values are expected to be echoed back to this adapter alongside any downstream response messages,
   * and are then prepended to the RID and BID field to restore the original identifier.
   *
-  * @param idBits is the desired number of AXID bits to be used
+  * @param idBits is the desired number of A[W|R]ID bits to be used
   */
 class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
 {

diff --git a/src/main/scala/amba/axi4/UserYanker.scala b/src/main/scala/amba/axi4/UserYanker.scala
@@ -12,9 +12,9 @@ import freechips.rocketchip.util._
   * storing them in queues and echoing them back when matching response messages are recevied.
   *
   * It also optionally rate limits the number of transactions that can be in flight simultaneously
-  * per FIFO domain / AXID.
+  * per FIFO domain / A[W|R]ID.
   *
-  * @param capMaxFlight is an optional maximum number of transactions that can be in flight per AXID.
+  * @param capMaxFlight is an optional maximum number of transactions that can be in flight per A[W|R]ID.
   */
 class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
 {