feat: convert groundtest to chisel3

Convert groundtest subdirectory to chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

src/main/scala/groundtest/DummyPTW.scala

@@ -3,7 +3,8 @@
 
 package freechips.rocketchip.groundtest
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket._
@@ -12,44 +13,44 @@ import freechips.rocketchip.util.ParameterizedBundle
 
 class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
-    val requestors = Vec(n, new TLBPTWIO).flip
+    val requestors = Flipped(Vec(n, new TLBPTWIO))
   }
 
   val req_arb = Module(new RRArbiter(Valid(new PTWReq), n))
   req_arb.io.in <> io.requestors.map(_.req)
-  req_arb.io.out.ready := Bool(true)
+  req_arb.io.out.ready := true.B
 
   def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
 
   class QueueChannel extends ParameterizedBundle()(p) {
-    val ppn = UInt(width = ppnBits)
-    val chosen = UInt(width = log2Up(n))
+    val ppn = UInt(ppnBits.W)
+    val chosen = UInt(log2Up(n).W)
   }
 
   val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.bits.addr)
   val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
   val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
-  val s2_valid = Reg(next = req_arb.io.out.valid && req_arb.io.out.bits.valid)
+  val s2_valid = RegNext(req_arb.io.out.valid && req_arb.io.out.bits.valid)
 
-  val s2_resp = Wire(init = 0.U.asTypeOf(new PTWResp))
+  val s2_resp = WireDefault(0.U.asTypeOf(new PTWResp))
   s2_resp.pte.ppn := s2_ppn
-  s2_resp.pte.reserved_for_software := UInt(0)
-  s2_resp.level := UInt(pgLevels-1)
-  s2_resp.pte.d := Bool(true)
-  s2_resp.pte.a := Bool(true)
-  s2_resp.pte.g := Bool(false)
-  s2_resp.pte.u := Bool(true)
-  s2_resp.pte.r := Bool(true)
-  s2_resp.pte.w := Bool(true)
-  s2_resp.pte.x := Bool(false)
-  s2_resp.pte.v := Bool(true)
+  s2_resp.pte.reserved_for_software := 0.U
+  s2_resp.level := (pgLevels-1).U
+  s2_resp.pte.d := true.B
+  s2_resp.pte.a := true.B
+  s2_resp.pte.g := false.B
+  s2_resp.pte.u := true.B
+  s2_resp.pte.r := true.B
+  s2_resp.pte.w := true.B
+  s2_resp.pte.x := false.B
+  s2_resp.pte.v := true.B
 
   io.requestors.zipWithIndex.foreach { case (requestor, i) =>
-    requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
+    requestor.resp.valid := s2_valid && s2_chosen === i.U
     requestor.resp.bits := s2_resp
     requestor.status := 0.U.asTypeOf(requestor.status)
     requestor.ptbr.mode := requestor.ptbr.pgLevelsToMode(pgLevels).U
-    requestor.ptbr.asid := UInt(0)
-    requestor.ptbr.ppn := UInt(0)
+    requestor.ptbr.asid := 0.U
+    requestor.ptbr.ppn := 0.U
   }
 }

src/main/scala/groundtest/GroundTestSubsystem.scala

@@ -2,8 +2,7 @@
 
 package freechips.rocketchip.groundtest
 
-import Chisel._
-import chisel3.dontTouch
+import chisel3._
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.diplomacy.{AddressSet, LazyModule}
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
@@ -30,7 +29,7 @@ class GroundTestSubsystem(implicit p: Parameters)
 }
 
 class GroundTestSubsystemModuleImp[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) {
-  val success = IO(Bool(OUTPUT))
+  val success = IO(Output(Bool()))
   val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle)))
   success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
 }

src/main/scala/groundtest/Status.scala

@@ -2,12 +2,13 @@
 
 package freechips.rocketchip.groundtest
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 import freechips.rocketchip.util.ValidMux
 
 class GroundTestStatus extends Bundle {
-  val timeout = Valid(UInt(width = 4))
-  val error = Valid(UInt(width = 4))
+  val timeout = Valid(UInt(4.W))
+  val error = Valid(UInt(4.W))
 }
 
 object DebugCombiner {

src/main/scala/groundtest/TestHarness.scala

@@ -2,13 +2,13 @@
 
 package freechips.rocketchip.groundtest
 
-import Chisel._
+import chisel3._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.system.SimAXIMem
 
 class TestHarness(implicit p: Parameters) extends Module {
-  val io = new Bundle { val success = Bool(OUTPUT) }
+  val io = new Bundle { val success = Output(Bool()) }
   val ldut = LazyModule(new GroundTestSubsystem)
   val dut = Module(ldut.module)
   io.success := dut.success

src/main/scala/groundtest/Tile.scala

@@ -3,7 +3,7 @@
 
 package freechips.rocketchip.groundtest
 
-import Chisel._
+import chisel3._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._