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BEU report Corrupt+Denied on I-Fetch #2482

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merged 2 commits into from
May 21, 2020
Merged

BEU report Corrupt+Denied on I-Fetch #2482

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5995627
BEU ICacheErrors TileLink bus I$ D-channel corrupt or denied
ingallsj May 21, 2020
ae60ff3
ICache bus error D-Channel address match A-Channel request
ingallsj May 21, 2020
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3 changes: 3 additions & 0 deletions src/main/scala/rocket/ICache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
with CanHaveErrors {
val correctable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(width = paddrBits)))
val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataCode.canDetect).option(Valid(UInt(width = paddrBits)))
val bus = Valid(UInt(width = paddrBits))
}

class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parameters) extends LazyModule {
Expand Down Expand Up @@ -220,6 +221,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)

ccover(tl_out.d.bits.corrupt, "D_CORRUPT", "I$ D-channel corrupt")
}
io.errors.bus.valid := tl_out.d.fire() && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
io.errors.bus.bits := (refill_paddr >> blockOffBits) << blockOffBits

val vb_array = Reg(init=Bits(0, nSets*nWays))
when (refill_one_beat) {
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7 changes: 4 additions & 3 deletions src/main/scala/tile/BusErrorUnit.scala
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Expand Up @@ -24,11 +24,12 @@ class L1BusErrors(implicit p: Parameters) extends CoreBundle()(p) with BusErrors
val icache = new ICacheErrors
val dcache = new DCacheErrors

def toErrorList = List(None, None,
icache.correctable.map((_, "I_CORRECTABLE", "Instruction cache or ITIM correctable ECC error ")),
def toErrorList = List(None,
Some((icache.bus, "IBUS", "Instruction cache TileLink bus error")),
icache.correctable.map((_, "I_CORRECTABLE", "Instruction cache or ITIM correctable ECC error")),
icache.uncorrectable.map((_, "I_UNCORRECTABLE", "ITIM uncorrectable ECC error")),
None,
Some((dcache.bus, "DBUS", "Load or store TileLink bus error")),
Some((dcache.bus, "DBUS", "Load/Store/PTW TileLink bus error")),
dcache.correctable.map((_, "D_CORRECTABLE", "Data cache correctable ECC error")),
dcache.uncorrectable.map((_, "D_UNCORRECTABLE", "Data cache uncorrectable ECC error")))
}
Expand Down