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Remove PutPartial from DMIToTL #2598

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Aug 10, 2020
Merged

Remove PutPartial from DMIToTL #2598

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7 changes: 3 additions & 4 deletions src/main/scala/devices/debug/DMI.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -83,8 +83,7 @@ class DMIToTL(implicit p: Parameters) extends LazyModule {
name = "debug",
emits = TLMasterToSlaveTransferSizes(
get = TransferSizes(4,4),
putFull = TransferSizes(4,4),
putPartial = TransferSizes(4,4)))))))
putFull = TransferSizes(4,4)))))))

lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {
Expand All @@ -100,13 +99,13 @@ class DMIToTL(implicit p: Parameters) extends LazyModule {
val (_, gbits) = edge.Get(src, addr, size)
val (_, pfbits) = edge.Put(src, addr, size, io.dmi.req.bits.data)

// We force DMI NOPs to go to CONTROL register because
// We force DMI NOPs to write to read-only HARTINFO register because
// Inner may be in reset / not have a clock,
// so we force address to be the one that goes to Outer.
// Therefore for a NOP we don't really need to pay the penalty to go
// across the CDC.

val (_, nbits) = edge.Put(src, toAddress = (DMI_RegAddrs.DMI_DMCONTROL << 2).U, size, data=0.U, mask = 0.U)
val (_, nbits) = edge.Put(src, toAddress = (DMI_RegAddrs.DMI_HARTINFO << 2).U, size, data=0.U)

when (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE) { tl.a.bits := pfbits
}.elsewhen (io.dmi.req.bits.op === DMIConsts.dmi_OP_READ) { tl.a.bits := gbits
Expand Down
44 changes: 23 additions & 21 deletions src/main/scala/devices/debug/Debug.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -297,6 +297,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod

val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++
AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOW << 2, 4),
device = device,
Expand Down Expand Up @@ -366,6 +367,16 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive
}

//----HARTINFO

val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}

//--------------------------------------------------------------
// Hart array mask and window
// HAMASK is 1 bit per component
Expand Down Expand Up @@ -503,17 +514,26 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
RegFieldDesc("haltreq", "halt request", reset=Some(0)))
))

val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(DsbRegAddrs.DATA))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(1))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(cfg.nScratch)))
))

//--------------------------------------------------------------
// DMI register decoder for Outer
//--------------------------------------------------------------
// regmap addresses are byte offsets from lowest address
def DMI_DMCONTROL_OFFSET = 0
def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)
def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)
def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)

val omRegMap = dmiNode.regmap(
DMI_DMCONTROL_OFFSET -> dmControlRegFields,
DMI_HARTINFO_OFFSET -> hartinfoRegFields,
DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(
WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,
RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil),
Expand Down Expand Up @@ -680,9 +700,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2

val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HAWINDOWSEL, HAWINDOW which are handled by Outer
// Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
Expand Down Expand Up @@ -1036,16 +1057,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
io.hgDebugInt := hgDebugInt | hrDebugInt


//----HARTINFO

val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}

//----HALTSUM*
val numHaltedStatus = ((nComponents - 1) / 32) + 1
val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))
Expand Down Expand Up @@ -1271,14 +1282,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
else RegField(4)
))

val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(DsbRegAddrs.DATA))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(1))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(cfg.nScratch)))
))

val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq(
RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField(4),
Expand All @@ -1302,7 +1305,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
(DMI_DMSTATUS << 2) -> dmstatusRegFields,
//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
(DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),
(DMI_HARTINFO << 2) -> hartinfoRegFields,
(DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"),
Seq(RegField.r(32, HALTSUM0RdData.asUInt(), RegFieldDesc("dmi_haltsum0", "halt summary 0")))),
(DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"),
Expand Down