Make SimAXIMem start at expected memory base instead of zero #2628
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KireinaHoro
changed the title
hcook
reviewed
Sep 4, 2020
|
Hmm, I have no idea why the test failed; it passed before the default parameter change and the logs aren't so obvious about exactly what failed |
hcook
approved these changes
Sep 23, 2020
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Type of change: feature request
Impact: no functional change
Development Phase: implementation
Release Notes
SimAXIMemcurrently assumes physical memory always starts at zero; this is not the case as it is possible to modifyp(ExtMem).get.master.basefor scenarios where the memory does not actually start there (e.g. when instantiating on Zynq FPGA and using the upper half of DRAM). This change adds support for this situation by reading the base ofExtMemandExtBusfrom the parameters for instantiation.